clipper.md

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;;
;; loadb  mem to reg
;; storb  reg to mem
;;
(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM && 
      ! register_operand (operands[1], QImode))
    operands[1] = force_reg (QImode, operands[1]);
}")


(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
	(match_operand:QI 1 "general_operand"   "r,m,n"))]
  ""
  "@
   movw   %1,%0
   loadb  %1,%0
   loadi  %1,%0"
[(set_attr "type" "arith,load,arith")])

(define_insn ""
  [(set (match_operand:QI 0 "memory_operand" "=m")
	(match_operand:QI 1 "register_operand" "r"))]
  ""
  "storb  %1,%0"
[(set_attr "type" "store")])


;;
;; block move
;;
(define_expand "movstrsi"
  [(parallel
    [(set (match_operand:BLK 0 "memory_operand" "")
          (match_operand:BLK 1 "memory_operand" ""))
     (use (match_operand:SI 2 "general_operand" ""))
     (use (match_operand:SI 3 "const_int_operand" ""))
     (clobber (match_scratch:SI 4 ""))
     (clobber (match_scratch:SI 5 ""))
     (clobber (match_dup 6))
     (clobber (match_dup 7))])]
  ""
  "
{
  rtx addr0, addr1;

  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));

  operands[6] = addr0;
  operands[7] = addr1;

  operands[0] = change_address (operands[0], VOIDmode, addr0);
  operands[1] = change_address (operands[1], VOIDmode, addr1);

  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = force_reg (SImode, operands[2]);
}")

;;
;; there is a problem with this insn in gcc-2.2.3
;; (clobber (match_dup 2)) does not prevent use of this operand later
;; we always use a scratch register and leave operand 2 unchanged
;;
(define_insn ""
  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
	(mem:BLK (match_operand:SI 1 "register_operand" "r")))
   (use (match_operand:SI 2 "nonmemory_operand" "rn"))
   (use (match_operand:SI 3 "const_int_operand" "n"))
   (clobber (match_scratch:SI 4 "=r"))
   (clobber (match_scratch:SI 5 "=r"))
   (clobber (match_dup 0))
   (clobber (match_dup 1))]
  ""
  "*
{
  extern void clipper_movstr ();
  clipper_movstr (operands);
  return \"\";
}"
[(set_attr "cc" "clobber")])



;; Extension and truncation insns.
(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $65535,%0\;xori   $32768,%0\;subi   $32768,%0
   loadh  %1,%0"
[(set_attr "type" "arith,load")])


(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $255,%0\;xori   $128,%0\;subi   $128,%0
   loadb  %1,%0"
[(set_attr "type" "arith,load")
 (set_attr "cc" "set1,change0")])


(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $255,%0\;xori   $128,%0\;subi   $128,%0
   loadb  %1,%0"
[(set_attr "type" "arith,load")])


(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
  ""
  "cnvsd  %1,%0")

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
  ""
  "cnvds  %1,%0")

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $65535,%0
   loadhu %1,%0"
[(set_attr "type" "arith,load")])


(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $255,%0
   loadbu %1,%0"
[(set_attr "type" "arith,load")
 (set_attr "cc" "clobber,clobber")])


(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
  ""
  "@
   andi   $255,%0
   loadbu %1,%0"
[(set_attr "type" "arith,load")])



;; Fix-to-float conversion insns.

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
  ""
  "cnvws  %1,%0")

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
  ""
  "cnvwd  %1,%0")


;; Float-to-fix conversion insns.

(define_insn "fix_truncsfsi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
  ""
  "cnvtsw %1,%0")

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
  ""
  "cnvtdw %1,%0")

;;- All kinds of add instructions.

(define_insn "adddf3"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
		 (match_operand:DF 2 "fp_reg_operand" "f")))]
  ""
  "addd   %2,%0"
 [(set_attr "type" "fp")])


(define_insn "addsf3"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
		 (match_operand:SF 2 "fp_reg_operand" "f")))]
  ""
  "adds   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "adddi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
		 (match_operand:DI 2 "int_reg_operand" "r")))]
  ""
  "*
{
  rtx xoperands[4];

  xoperands[0] = operands[0];
  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  xoperands[2] = operands[2];
  xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  output_asm_insn (\"addw   %2,%0\;addwc  %3,%1\", xoperands);
  return \"\";
}"
[(set_attr "type" "arith")
 (set_attr "cc" "clobber")])

(define_insn "addsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
	(plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
		 (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
  ""
  "*
{
  if (which_alternative == 2)		/* 3 address version */
    {
      if (GET_CODE (operands[2]) == CONST_INT)
	return \"loada  %a2(%1),%0\";
      return \"loada  [%2](%1),%0\";
    }
					/* 2 address version */
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int val = INTVAL (operands[2]);

      if (val >= 16 || val == 0x80000000)
	return \"addi   %2,%0\";

      if (val < 0)			/* change to sub */
	{
	  rtx xops[2];

	  val = -val;

	  xops[0] = operands[0];
	  xops[1] = GEN_INT (val);

	  if (val >= 16)
	    output_asm_insn (\"subi   %1,%0\", xops);
	  else
	    output_asm_insn (\"subq   %1,%0\", xops);

	  return \"\";
	}

      return \"addq   %2,%0\";
    }

  if (which_alternative == 0)
    return \"addw   %2,%0\";

  return \"addw   %1,%0\";
}"
[(set_attr "type" "arith,arith,arith")
 (set_attr "cc" "set1,set1,change0")])


;;- All kinds of subtract instructions.

(define_insn "subdi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(minus:DI (match_operand:DI 1 "int_reg_operand" "0")
		  (match_operand:DI 2 "int_reg_operand" "r")))]
  ""
  "*
{
  rtx xoperands[4];

  xoperands[0] = operands[0];
  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  xoperands[2] = operands[2];
  xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  output_asm_insn (\"subw   %2,%0\;subwc  %3,%1\", xoperands);
  return \"\";
}"
[(set_attr "type" "arith")
 (set_attr "cc" "clobber")])

(define_insn "subsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(minus:SI (match_operand:SI 1 "int_reg_operand" "0")
		  (match_operand:SI 2 "nonmemory_operand" "rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int val = INTVAL (operands[2]);

      if (val < 0 || val >= 16)
	return \"subi   %2,%0\";
      else
	return \"subq   %2,%0\";
    }

  return \"subw   %2,%0\";
}"
[(set_attr "type" "arith")])

(define_insn "subdf3"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
		  (match_operand:DF 2 "fp_reg_operand" "f")))]
  ""
  "subd   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "subsf3"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
		  (match_operand:SF 2 "fp_reg_operand" "f")))]
  ""
  "subs   %2,%0"
 [(set_attr "type" "fp")])


;;- Multiply instructions.

(define_insn "muldf3"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
		 (match_operand:DF 2 "fp_reg_operand" "f")))]
  ""
  "muld   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
		 (match_operand:SF 2 "fp_reg_operand" "f")))]
  ""
  "muls   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
	         (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
  ""
  "mulwx  %2,%0"
[(set_attr "type" "arith")
 (set_attr "cc" "clobber")])

(define_insn "umulsidi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
	         (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
  ""
  "mulwux %2,%0"
[(set_attr "type" "arith")
 (set_attr "cc" "clobber")])

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
	         (match_operand:SI 2 "int_reg_operand" "r")))]
  ""
  "mulw   %2,%0"
 [(set_attr "type" "arith")
  (set_attr "cc" "clobber")])


;;- Divide and mod instructions.

(define_insn "divdf3"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(div:DF (match_operand:DF 1 "fp_reg_operand" "0")
		(match_operand:DF 2 "fp_reg_operand" "f")))]
  ""
  "divd   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "divsf3"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(div:SF (match_operand:SF 1 "fp_reg_operand" "0")
		(match_operand:SF 2 "fp_reg_operand" "f")))]
  ""
  "divs   %2,%0"
 [(set_attr "type" "fp")])

(define_insn "divsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(div:SI (match_operand:SI 1 "int_reg_operand" "0")
		(match_operand:SI 2 "int_reg_operand" "r")))]
  ""
  "divw   %2,%0"
 [(set_attr "type" "arith")
  (set_attr "cc" "clobber")])

(define_insn "udivsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
	         (match_operand:SI 2 "int_reg_operand" "r")))]
  ""
  "divwu  %2,%0"
 [(set_attr "type" "arith")
  (set_attr "cc" "clobber")])


(define_insn "modsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(mod:SI (match_operand:SI 1 "int_reg_operand" "0")
		(match_operand:SI 2 "int_reg_operand" "r")))]
  ""
  "modw   %2,%0"
 [(set_attr "type" "arith")
  (set_attr "cc" "clobber")])

(define_insn "umodsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(umod:SI (match_operand:SI 1 "int_reg_operand" "0")
	         (match_operand:SI 2 "int_reg_operand" "r")))]
  ""
  "modwu  %2,%0"
 [(set_attr "type" "arith")
  (set_attr "cc" "clobber")])

;;
;; bit and/or instructions
;;
(define_insn "andsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
        (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   andw   %2,%0
   andi   %2,%0"
 [(set_attr "type" "arith")])

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
	        (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   orw    %2,%0
   ori    %2,%0"
 [(set_attr "type" "arith")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   xorw   %2,%0
   xori   %2,%0"