elxsi.md

gcc编译工具没有什么特别

	(minus:SF (match_operand:SF 1 "general_operand" "0")
		  (match_operand:SF 2 "general_operand" "rm")))]
  ""
  "fsub.32\\t%0,%2")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
	(minus:DI (match_operand:DI 1 "general_operand" "0,g,r")
		  (match_operand:DI 2 "general_operand" "g,r,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"sub.64\\t%0,%2\";
    else if (which_alternative == 1)
      return \"subr.64\\t%0,%2,%1\";
    else
      return \"sub.64\\t%0,%1,%2\";
")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
		  (match_operand:SI 2 "general_operand" "m,r,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"sub.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"subr.32\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"sub.32\\t%0,%1,%2\";
    else
      return \"sub.64\\t%0,%2 ; I only want 32\";
")

(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
	(minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0")
		  (match_operand:HI 2 "general_operand" "m,r,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"sub.16\\t%0,%2\";
    else if (which_alternative == 1)
      return \"subr.16\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"sub.16\\t%0,%1,%2\";
    else
      return \"sub.64\\t%0,%2 ; I only want 16\";
")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(mult:DF (match_operand:DF 1 "general_operand" "%0")
		 (match_operand:DF 2 "general_operand" "rm")))]
  ""
  "fmul.64\\t%0,%2")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(mult:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "rm")))]
  ""
  "fmul.32\\t%0,%2")

(define_insn "muldi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(mult:DI (match_operand:DI 1 "general_operand" "%0,r")
		 (match_operand:DI 2 "general_operand" "g,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"mul.64\\t%0,%2\";
    return \"mul.64\\t%0,%1,%2\";
")

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(mult:SI (match_operand:SI 1 "general_operand" "%0,r,0")
		 (match_operand:SI 2 "general_operand" "m,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"mul.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"mul.32\\t%0,%1,%2\";
    else
      return \"mul.64\\t%0,%2 ; I only want 32\";
")

(define_insn "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(mult:HI (match_operand:HI 1 "general_operand" "%0,r,0")
		 (match_operand:HI 2 "general_operand" "m,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"mul.16\\t%0,%2\";
    else if (which_alternative == 1)
      return \"mul.16\\t%0,%1,%2\";
    else
      return \"mul.64\\t%0,%2 ; I only want 16\";
")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(div:DF (match_operand:DF 1 "general_operand" "0")
		(match_operand:DF 2 "general_operand" "rm")))]
  ""
  "fdiv.64\\t%0,%2")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(div:SF (match_operand:SF 1 "general_operand" "0")
		(match_operand:SF 2 "general_operand" "rm")))]
  ""
  "fdiv.32\\t%0,%2")

(define_insn "divdi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
	(div:DI (match_operand:DI 1 "general_operand" "0,g,r")
		(match_operand:DI 2 "general_operand" "g,r,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"div.64\\t%0,%2\";
    else if (which_alternative == 1)
      return \"divr.64\\t%0,%2,%1\";
    else
      return \"div.64\\t%0,%1,%2\";
")

(define_insn "divsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(div:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
/* We don't ignore high bits. */
if (0) {
    if (which_alternative == 0)
      return \"div.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"divr.32\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"div.32\\t%0,%1,%2\";
    else
      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
} else {
    if (which_alternative == 0)
      return \"ld.32\\t%0,%0\;div.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\";
    else
      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
}
")

(define_insn "divhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
	(div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\";
    else if (which_alternative == 1)
      return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\";
    else if (which_alternative == 3)
      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
    else
      return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
")

(define_insn "modhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
	(mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\";
    else if (which_alternative == 1)
      return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\";
    else if (which_alternative == 3)
      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
    else
      return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
")

(define_insn "moddi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
	(mod:DI (match_operand:DI 1 "general_operand" "0,g,r")
		(match_operand:DI 2 "general_operand" "g,r,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
    if (which_alternative == 0)
      return \"rem.64\\t%0,%2\";
    else if (which_alternative == 1)
      return \"remr.64\\t%0,%2,%1\";
    else
      return \"rem.64\\t%0,%1,%2\";
")

(define_insn "modsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
  "*
/* There is a micro code bug with the below... */
if (0) {
    if (which_alternative == 0)
      return \"rem.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"remr.32\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"rem.32\\t%0,%1,%2\";
    else
      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
} else {
    if (which_alternative == 0)
      return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\";
    else if (which_alternative == 1)
      return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\";
    else if (which_alternative == 2)
      return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\";
    else
      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
}
")


(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jmp\\t%l0")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
  ""
;; Maybe %l0 is better, maybe we can relax register only.
  "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0")

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 2, operands[0]); ")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 8, operands[0]); ")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 0, operands[0]); ")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"u\", 0, operands[0]); ")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 6, operands[0]); ")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"u\", 6, operands[0]); ")

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 4, operands[0]); ")

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"u\", 4, operands[0]); ")

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"\", 10, operands[0]); ")

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return cmp_jmp(\"u\", 10, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 8, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 2, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 10, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gtu (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"u\", 10, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 4, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ltu (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"u\", 4, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 6, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (geu (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"u\", 6, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"\", 0, operands[0]); ")

(define_insn ""
  [(set (pc)
	(if_then_else (leu (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return cmp_jmp(\"u\", 0, operands[0]); ")

;; Note that operand 1 is total size of args, in bytes,
;; and what the call insn wants is the number of words.
(define_insn "call"
  [(call (match_operand:QI 0 "general_operand" "m")
	 (match_operand:QI 1 "general_operand" "g"))]
  ""
  "*
  if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG)
    if (REGNO (XEXP (operands[0], 0)) != 0)
      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
    else
      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
  else
    return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
  ")

(define_insn "call_value"
  [(set (match_operand 0 "" "g")
	(call (match_operand:QI 1 "general_operand" "m")
	      (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
  if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG)
    if (REGNO (XEXP (operands[1], 0)) != 0)
      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
    else
      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
  else
    return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
  ")

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "br.reg\\t%0")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")