ns32k.h

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/* Definitions of target machine for GNU compiler.  NS32000 version.
   Copyright (C) 1988, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
   Contributed by Michael Tiemann ([e-mail])

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */


/* Note that some other tm.h files include this one and then override
   many of the definitions that relate to assembler syntax.  */

/* Names to predefine in the preprocessor for this target machine.  */

#define CPP_PREDEFINES "-Dns32000 -Dunix -Asystem(unix) -Acpu(ns32k) -Amachine(ns32k)"

/* Print subsidiary information on the compiler version in use.  */
#define TARGET_VERSION fprintf (stderr, " (32000, GAS syntax)");


/* ABSOLUTE PREFIX, IMMEDIATE_PREFIX and EXTERNAL_PREFIX can be defined
   to cover most NS32k addressing syntax variations.  This way we don't
   need to redefine long macros in all the tm.h files for just slight
   variations in assembler syntax. */

#ifndef ABSOLUTE_PREFIX
#define ABSOLUTE_PREFIX '@'
#endif

#if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX
#define PUT_IMMEDIATE_PREFIX(FILE) putc(IMMEDIATE_PREFIX, FILE)
#else
#define PUT_IMMEDIATE_PREFIX(FILE)
#endif
#if defined(ABSOLUTE_PREFIX) && ABSOLUTE_PREFIX
#define PUT_ABSOLUTE_PREFIX(FILE) putc(ABSOLUTE_PREFIX, FILE)
#else
#define PUT_ABSOLUTE_PREFIX(FILE)
#endif
#if defined(EXTERNAL_PREFIX) && EXTERNAL_PREFIX
#define PUT_EXTERNAL_PREFIX(FILE) putc(EXTERNAL_PREFIX, FILE)
#else
#define PUT_EXTERNAL_PREFIX(FILE)
#endif

/* Run-time compilation parameters selecting different hardware subsets.  */

extern int target_flags;

/* Macros used in the machine description to test the flags.  */

/* Compile 32081 insns for floating point (not library calls). */
#define TARGET_32081 (target_flags & 1)
#define TARGET_32381 (target_flags & 256)

/* The use of multiply-add instructions is optional because it can
 * cause an abort due to being unable to find a spill register. The
 * main problem is that the multiply-add instructions require f0 and
 * f0 is not available for spilling because it is "explicitly
 * mentioned" in the rtl for function return values. This can be fixed
 * by defining SMALL_REGISTER_CLASSES, but that causes worse code for
 * the (more common) integer case. We really need better reload code.
 */

#define TARGET_MULT_ADD (target_flags & 512)

/* Compile using rtd insn calling sequence.
   This will not work unless you use prototypes at least
   for all functions that can take varying numbers of args.  */
#define TARGET_RTD (target_flags & 2)

/* Compile passing first two args in regs 0 and 1.  */
#define TARGET_REGPARM (target_flags & 4)

/* Options to select type of CPU, for better optimization.
   The output is correct for any kind of 32000 regardless of these options.  */
#define TARGET_32532 (target_flags & 8)
#define TARGET_32332 (target_flags & 16)

/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB    ((target_flags & 32) == 0)
#define TARGET_HIMEM (target_flags & 128)

/* Compile using bitfield insns.  */
#define TARGET_BITFIELD ((target_flags & 64) == 0)

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES				\
  { { "32081", 1},				\
    { "soft-float", -257},			\
    { "rtd", 2},				\
    { "nortd", -2},				\
    { "regparm", 4},				\
    { "noregparm", -4},				\
    { "32532", 24},				\
    { "32332", -8},				\
    { "32332", 16},				\
    { "32032", -24},				\
    { "sb", -32},				\
    { "nosb", 32},				\
    { "bitfield", -64},				\
    { "nobitfield", 64},			\
    { "himem", 128},				\
    { "nohimem", -128},				\
    { "32381", 256},				\
    { "mult-add", 512},				\
    { "nomult-add", -512},            		\
    { "", TARGET_DEFAULT}}

/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc.  */

/* When we are generating PIC, the sb is used as a pointer
   to the GOT. 32381 is a superset of 32081  */

#define OVERRIDE_OPTIONS				\
{							\
  if (flag_pic || TARGET_HIMEM) target_flags |= 32;	\
  if (TARGET_32381) target_flags |= 1;			\
  else target_flags &= ~512;				\
}

/* Zero or more C statements that may conditionally modify two
   variables `fixed_regs' and `call_used_regs' (both of type `char
   []') after they have been initialized from the two preceding
   macros.

   This is necessary in case the fixed or call-clobbered registers
   depend on target flags.

   You need not define this macro if it has no work to do.

   If the usage of an entire class of registers depends on the target
   flags, you may indicate this to GCC by using this macro to modify
   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
   the classes which should not be used by GCC.  Also define the macro
   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
   letter for a class that shouldn't be used.

   (However, if this class is not included in `GENERAL_REGS' and all
   of the insn patterns whose constraints permit this class are
   controlled by target switches, then GCC will automatically avoid
   using these registers when the target switches are opposed to
   them.)  */

#define CONDITIONAL_REGISTER_USAGE					\
do									\
  {									\
    if (!TARGET_32081)						\
      {									\
	int regno;							\
									\
	for (regno = F0_REGNUM; regno <= F0_REGNUM + 8; regno++)	\
	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
      }									\
    if (!TARGET_32381)						\
      {									\
	int regno;							\
									\
	for (regno = L1_REGNUM; regno <= L1_REGNUM + 8; regno++)	\
	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
      }									\
  }									\
while (0)


/* target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   This is not true on the ns32k.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is not true on the ns32k.  */
#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is lowest
   numbered. This is not true on the ns32k.  */
#define WORDS_BIG_ENDIAN 0

/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 32000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 32

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* Every structure's size must be a multiple of this.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT 32

/* Set this nonzero if move instructions will actually fail to work
   when given unaligned data.  National claims that the NS32032
   works without strict alignment, but rumor has it that operands
   crossing a page boundary cause unpredictable results.  */
#define STRICT_ALIGNMENT 1

/* If bit field type is int, dont let it cross an int,
   and give entire struct the alignment of an int.  */
/* Required on the 386 since it doesn't have a full set of bitfield insns.
   (There is no signed extv insn.)  */
#define PCC_BITFIELD_TYPE_MATTERS 1

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.  */
#define FIRST_PSEUDO_REGISTER 26

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.
   On the ns32k, these are the FP, SP, (SB and PC are not included here).  */
#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, \
			 0, 0, 0, 0, 0, 0, 0, 0, \
                         0, 0, 0, 0, 0, 0, 0, 0, \
			 1, 1}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, \
			     1, 1, 1, 1, 0, 0, 0, 0, \
			     1, 1, 0, 0, 0, 0, 0, 0, \
			     1, 1}

/* How to refer to registers in assembler output.
   This sequence is indexed by compiler's hard-register-number (see above).  */

#define REGISTER_NAMES \
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
 "l1", "l1h","l3", "l3h","l5", "l5h","l7", "l7h", \
 "fp", "sp"}


#define ADDITIONAL_REGISTER_NAMES \
{{"l0", 8}, {"l2", 10}, {"l4", 12}, {"l6", 14}}

/* l0-7 are not recognized by the assembler. These are the names to use,
 * but we don't want ambiguous names in REGISTER_NAMES
 */
#define OUTPUT_REGISTER_NAMES \
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
 "f1", "l1h","f3", "l3h","f5", "l5h","f7", "f7h", \
 "fp", "sp"}

#define REG_ALLOC_ORDER \
{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 10, 11, 18, 12, 13, 20, 14, 15, 22, 24, 25, 17, 19, 23}

/* How to renumber registers for dbx and gdb.
   NS32000 may need more change in the numeration. XXX */

#define DBX_REGISTER_NUMBER(REGNO) \
  ((REGNO) < L1_REGNUM? (REGNO) \
   : (REGNO) < FRAME_POINTER_REGNUM? (REGNO) - L1_REGNUM + 22 \
   : (REGNO) == FRAME_POINTER_REGNUM? 17 \
   : 16)




#define R0_REGNUM 0
#define F0_REGNUM 8
#define L1_REGNUM 16

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* NS32000 pc is not overloaded on a register.  */
/* #define PC_REGNUM */

/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM 25

/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 24


/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.
   On the ns32k, all registers are 32 bits long except for the 32381 "long"
   registers but we treat those as pairs  */
#define LONG_FP_REGS_P(REGNO) ((REGNO) >= L1_REGNUM && (REGNO) < L1_REGNUM + 8)
#define HARD_REGNO_NREGS(REGNO, MODE)   \
 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok (REGNO, MODE)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.

   Early documentation says SI and DI are not tieable if some reg can