basysrevedemo.par

actel BASYs开发板自带的demo程序

Release 8.2.02i par I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

PROGRAMMING::  Tue Dec 05 21:58:53 2006

par -w -intstyle ise -ol std -t 1 BasysRevEDemo_map.ncd BasysRevEDemo.ncd
BasysRevEDemo.pcf 


Constraints file: BasysRevEDemo.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx.
   "BasysRevEDemo" is an NCD, version 3.1, device xc3s100e, package tq144, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.26 2006-07-12".


Design Summary Report:

 Number of External IOBs                          46 out of 108    42%

   Number of External Input IOBs                 14

      Number of External Input IBUFs             14
        Number of LOCed External Input IBUFs     14 out of 14    100%


   Number of External Output IOBs                30

      Number of External Output IOBs             30
        Number of LOCed External Output IOBs     30 out of 30    100%


   Number of External Bidir IOBs                  2

      Number of External Bidir IOBs               2
        Number of LOCed External Bidir IOBs       2 out of 2     100%


   Number of BUFGMUXs                  7 out of 24     29%
   Number of DCMs                      1 out of 2      50%
   Number of Slices                  864 out of 960    90%
      Number of SLICEMs                0 out of 480     0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98bf0b) REAL time: 7 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 7 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 7 secs 

Phase 4.2
......
.........................


Phase 4.2 (Checksum:98c573) REAL time: 13 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 13 secs 

Phase 6.8
.....................................................................................................
...............
..................................................................................................
......................
............................
......
Phase 6.8 (Checksum:b1272d) REAL time: 24 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 24 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 30 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 30 secs 

Writing design to file BasysRevEDemo.ncd


Total REAL time to Placer completion: 31 secs 
Total CPU time to Placer completion: 28 secs 

Starting Router

Phase 1: 6065 unrouted;       REAL time: 32 secs 

Phase 2: 5651 unrouted;       REAL time: 32 secs 

Phase 3: 1595 unrouted;       REAL time: 33 secs 

Phase 4: 1595 unrouted; (292693)      REAL time: 33 secs 

Phase 5: 1719 unrouted; (27482)      REAL time: 34 secs 

Phase 6: 0 unrouted; (38117)      REAL time: 39 secs 

Phase 7: 0 unrouted; (38117)      REAL time: 40 secs 

Phase 8: 0 unrouted; (38117)      REAL time: 40 secs 

Phase 9: 0 unrouted; (38117)      REAL time: 40 secs 

WARNING:Route:447 - CLK Net:XLXI_175/cntDiv<21> may have excessive skew because 
   1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:XLXI_175/cntDiv<17> may have excessive skew because 
   1 NON-CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 40 secs 
Total CPU time to Router completion: 37 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| XLXI_175/cntDiv<17> | BUFGMUX_X1Y10| No   |   33 |  0.028     |  0.064      |
+---------------------+--------------+------+------+------------+-------------+
|             ck25MHz | BUFGMUX_X1Y11| No   |   26 |  0.019     |  0.056      |
+---------------------+--------------+------+------+------------+-------------+
|            ck100MHz | BUFGMUX_X2Y11| No   |  130 |  0.023     |  0.058      |
+---------------------+--------------+------+------+------------+-------------+
|          CLK1_BUFGP |  BUFGMUX_X2Y1| No   |   12 |  0.012     |  0.063      |
+---------------------+--------------+------+------+------------+-------------+
| XLXI_175/cntDiv<21> | BUFGMUX_X2Y10| No   |  130 |  0.030     |  0.064      |
+---------------------+--------------+------+------+------------+-------------+
|   XLXI_175/_not0021 |  BUFGMUX_X2Y0| No   |   21 |  0.028     |  0.063      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.883
   The MAXIMUM PIN DELAY IS:                               3.834
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.855

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        3810        1847         317          53           0           0

Timing Score: 37910

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net XLX | N/A        | 5.251ns    | 6      | N/A        | N/A     
  I_175/cntDiv<17>                          |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net CLK | N/A        | 5.521ns    | 4      | N/A        | N/A     
  1_BUFGP                                   |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net XLX | N/A        | 6.568ns    | 2      | N/A        | N/A     
  I_175/cntDiv<21>                          |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ck25MHz1" derive | N/A        | 7.482ns    | 3      | N/A        | N/A     
  d from  Autotimespec constraint for clock |            |            |        |            |         
   net XLXI_171/ck0Div2  multiplied by 2.00 |            |            |        |            |         
   and duty cycle corrected to 20 nS  HIGH  |            |            |        |            |         
  10 nS                                     |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ck100MHz1" deriv | N/A        | 6.174ns    | 7      | N/A        | N/A     
  ed from  Autotimespec constraint for cloc |            |            |        |            |         
  k net XLXI_171/ck0Div2  divided by 2.00 a |            |            |        |            |         
  nd duty cycle corrected to 5 nS  HIGH 2.5 |            |            |        |            |         
  00 nS                                     |            |            |        |            |         
------------------------------------------------------------------------------------------------------


1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 47 secs 
Total CPU time to PAR completion: 42 secs 

Peak Memory Usage:  157 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file BasysRevEDemo.ncd



PAR done!