basysrevedemo_map.mrp

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Release 8.2.02i Map I.33
Xilinx Mapping Report File for Design 'BasysRevEDemo'

Design Information
------------------
Command Line   : C:\Xilinx\bin\nt\map.exe -ise
C:/Projects/Basys_Projects/Basys_REVE/Demo/UncompiledBasysRevEDemo_12-04-06/Basy
sRevEDemo.ise -intstyle ise -p xc3s100e-tq144-5 -cm area -pr b -k 4 -c 100 -o
BasysRevEDemo_map.ncd BasysRevEDemo.ngd BasysRevEDemo.pcf 
Target Device  : xc3s100e
Target Package : tq144
Target Speed   : -5
Mapper Version : spartan3e -- $Revision: 1.34.32.1 $
Mapped Date    : Tue Dec 05 21:58:37 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:   17
Logic Utilization:
  Total Number Slice Registers:       622 out of   1,920   32%
    Number used as Flip Flops:                   587
    Number used as Latches:                       35
  Number of 4 input LUTs:           1,450 out of   1,920   75%
Logic Distribution:
  Number of occupied Slices:                          864 out of     960   90%
    Number of Slices containing only related logic:     864 out of     864  100%
    Number of Slices containing unrelated logic:          0 out of     864    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,566 out of   1,920   81%
  Number used as logic:              1,450
  Number used as a route-thru:         116
  Number of bonded IOBs:               46 out of     108   42%
    IOB Flip Flops:                     5
  Number of GCLKs:                     7 out of      24   29%
  Number of DCMs:                      1 out of       2   50%

Total equivalent gate count for design:  23,203
Additional JTAG gate count for IOBs:  2,208
Peak Memory Usage:  162 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network XLXN_524 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 17
   more times for the following (max. 5 shown):
   XLXI_66/CLKDLL_inst/CLK0,
   XLXI_66/CLKDLL_inst/CLK90,
   XLXI_66/CLKDLL_inst/CLK180,
   XLXI_66/CLKDLL_inst/CLK270,
   XLXI_66/CLKDLL_inst/CLK2X180
   To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_XLXI_175/cntDiv<17>/XLXI_175/cntDiv_17_BUFG" (output
   signal=XLXI_175/cntDiv<17>) has a mix of clock and non-clock loads. The
   non-clock loads are:
   Pin S of XLXI_175/Mcount_cntDiv_cy<17>
   Pin LI of XLXI_175/Mcount_cntDiv_xor<17>
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_XLXI_175/cntDiv<21>/XLXI_175/cntDiv_21_BUFG" (output
   signal=XLXI_175/cntDiv<21>) has a mix of clock and non-clock loads. The
   non-clock loads are:
   Pin LI of XLXI_175/Mcount_cntDiv_xor<21>
WARNING:Pack:266 - The function generator XLXI_172/AdrB<4>_mmx_out212 failed to
   merge with F5 multiplexer XLXI_172/AdrB<5>12_f5.  There is a conflict for the
   FXMUX.  The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator XLXI_172/AdrB<4>_mmx_out132 failed to
   merge with F5 multiplexer XLXI_172/AdrB<5>_mmx_out_f51.  There is a conflict
   for the GYMUX.  The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator XLXI_172/Mrom__rom00042 failed to
   merge with F5 multiplexer XLXI_172/AdrB<4>_mmx_out311_f5.  There is a
   conflict for the FXMUX.  The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   HSYNC/HSYNC is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaRed<0>/vgaRed<0> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaRed<1>/vgaRed<1> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaRed<2>/vgaRed<2> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   VSYNC/VSYNC is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaGreen<0>/vgaGreen<0> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaGreen<1>/vgaGreen<1> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaGreen<2>/vgaGreen<2> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaBlue<0>/vgaBlue<0> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   vgaBlue<1>/vgaBlue<1> is set but the tri state is not configured. 

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "CLK1_BUFGP" (output signal=CLK1_BUFGP),
   BUFG symbol "XLXI_175/_not0021_BUFG" (output signal=XLXI_175/_not0021),
   BUFG symbol "XLXI_175/cntDiv_17_BUFG" (output signal=XLXI_175/cntDiv<17>),
   BUFG symbol "XLXI_175/cntDiv_21_BUFG" (output signal=XLXI_175/cntDiv<21>),
   BUFG symbol "ck100MHz_BUFG" (output signal=ck100MHz),
   BUFG symbol "ck25MHz_BUFG" (output signal=ck25MHz)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   4 block(s) optimized away