basysrevedemo.twr

actel BASYs开发板自带的demo程序

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Release 8.2.02i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise
C:/Projects/Basys_Projects/Basys_REVE/Demo/UncompiledBasysRevEDemo_12-04-06/BasysRevEDemo.ise
-intstyle ise -e 3 -l 3 -s 5 -xml BasysRevEDemo BasysRevEDemo.ncd -o
BasysRevEDemo.twr BasysRevEDemo.pcf -ucf MainBasys.ucf

Design file:              basysrevedemo.ncd
Physical constraint file: basysrevedemo.pcf
Device,speed:             xc3s100e,-5 (PRODUCTION 1.26 2006-07-12)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK2
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
PS2C        |    2.419(R)|    1.236(R)|ck100MHz          |   0.000|
PS2D        |    2.419(R)|    1.069(R)|ck100MHz          |   0.000|
sw<7>       |    3.500(R)|   -1.944(R)|CLK2_IBUFG        |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK1 to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
an<0>       |   11.188(R)|CLK1_BUFGP        |   0.000|
an<1>       |   10.864(R)|CLK1_BUFGP        |   0.000|
an<2>       |   10.864(R)|CLK1_BUFGP        |   0.000|
an<3>       |   10.601(R)|CLK1_BUFGP        |   0.000|
dp          |   10.168(R)|CLK1_BUFGP        |   0.000|
led<0>      |   11.348(R)|CLK1_BUFGP        |   0.000|
led<1>      |   10.834(R)|CLK1_BUFGP        |   0.000|
led<2>      |   10.658(R)|CLK1_BUFGP        |   0.000|
led<3>      |   10.332(R)|CLK1_BUFGP        |   0.000|
led<4>      |   10.561(R)|CLK1_BUFGP        |   0.000|
led<5>      |   10.544(R)|CLK1_BUFGP        |   0.000|
led<6>      |   10.629(R)|CLK1_BUFGP        |   0.000|
led<7>      |   11.005(R)|CLK1_BUFGP        |   0.000|
seg<0>      |   19.319(R)|CLK1_BUFGP        |   0.000|
seg<1>      |   19.152(R)|CLK1_BUFGP        |   0.000|
seg<2>      |   18.379(R)|CLK1_BUFGP        |   0.000|
seg<3>      |   19.007(R)|CLK1_BUFGP        |   0.000|
seg<4>      |   18.993(R)|CLK1_BUFGP        |   0.000|
seg<5>      |   20.073(R)|CLK1_BUFGP        |   0.000|
seg<6>      |   18.025(R)|CLK1_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock CLK2 to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
HSYNC       |   12.492(R)|ck25MHz           |   0.000|
PS2C        |   10.075(R)|ck100MHz          |   0.000|
PS2D        |   10.075(R)|ck100MHz          |   0.000|
VSYNC       |    9.956(R)|ck25MHz           |   0.000|
vgaBlue<0>  |   26.423(R)|ck100MHz          |   0.000|
            |   26.355(R)|ck25MHz           |   0.000|
vgaBlue<1>  |   25.945(R)|ck100MHz          |   0.000|
            |   25.877(R)|ck25MHz           |   0.000|
vgaGreen<0> |   26.084(R)|ck100MHz          |   0.000|
            |   26.016(R)|ck25MHz           |   0.000|
vgaGreen<1> |   26.541(R)|ck100MHz          |   0.000|
            |   26.473(R)|ck25MHz           |   0.000|
vgaGreen<2> |   26.149(R)|ck100MHz          |   0.000|
            |   26.081(R)|ck25MHz           |   0.000|
vgaRed<0>   |   26.152(R)|ck100MHz          |   0.000|
            |   26.084(R)|ck25MHz           |   0.000|
vgaRed<1>   |   26.251(R)|ck100MHz          |   0.000|
            |   26.183(R)|ck25MHz           |   0.000|
vgaRed<2>   |   25.695(R)|ck100MHz          |   0.000|
            |   25.627(R)|ck25MHz           |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK1
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK1           |    5.521|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock CLK2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK2           |    7.482|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Dec 05 21:59:49 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 131 MB