map.xmsgs

actel BASYs开发板自带的demo程序

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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">XLXN_524</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">17</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">XLXI_66/CLKDLL_inst/CLK0,
XLXI_66/CLKDLL_inst/CLK90,
XLXI_66/CLKDLL_inst/CLK180,
XLXI_66/CLKDLL_inst/CLK270,
XLXI_66/CLKDLL_inst/CLK2X180</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol &quot;CLK1_BUFGP&quot; (output signal=CLK1_BUFGP),
BUFG symbol &quot;XLXI_175/_not0021_BUFG&quot; (output signal=XLXI_175/_not0021),
BUFG symbol &quot;XLXI_175/cntDiv_17_BUFG&quot; (output signal=XLXI_175/cntDiv&lt;17&gt;),
BUFG symbol &quot;XLXI_175/cntDiv_21_BUFG&quot; (output signal=XLXI_175/cntDiv&lt;21&gt;),
BUFG symbol &quot;ck100MHz_BUFG&quot; (output signal=ck100MHz),
BUFG symbol &quot;ck25MHz_BUFG&quot; (output signal=ck25MHz)</arg>
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_XLXI_175/cntDiv&lt;17&gt;/XLXI_175/cntDiv_17_BUFG&quot; (output signal=XLXI_175/cntDiv&lt;17&gt;)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin S of XLXI_175/Mcount_cntDiv_cy&lt;17&gt;
Pin LI of XLXI_175/Mcount_cntDiv_xor&lt;17&gt;</arg>
</msg>

<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_XLXI_175/cntDiv&lt;21&gt;/XLXI_175/cntDiv_21_BUFG&quot; (output signal=XLXI_175/cntDiv&lt;21&gt;)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin LI of XLXI_175/Mcount_cntDiv_xor&lt;21&gt;</arg>
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">XLXI_172/AdrB&lt;4&gt;_mmx_out212</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">XLXI_172/AdrB&lt;5&gt;12_f5</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">XLXI_172/AdrB&lt;4&gt;_mmx_out132</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">XLXI_172/AdrB&lt;5&gt;_mmx_out_f51</arg>.  <arg fmt="%z" index="3">There is a conflict for the GYMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">XLXI_172/Mrom__rom00042</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">XLXI_172/AdrB&lt;4&gt;_mmx_out311_f5</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp HSYNC/HSYNC is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaRed&lt;0&gt;/vgaRed&lt;0&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaRed&lt;1&gt;/vgaRed&lt;1&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaRed&lt;2&gt;/vgaRed&lt;2&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp VSYNC/VSYNC is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaGreen&lt;0&gt;/vgaGreen&lt;0&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaGreen&lt;1&gt;/vgaGreen&lt;1&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaGreen&lt;2&gt;/vgaGreen&lt;2&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaBlue&lt;0&gt;/vgaBlue&lt;0&gt; is set but the tri state is not configured. 
</msg>

<msg type="warning" file="PhysDesignRules" num="781">PULLUP on an active net. PULLUP of comp vgaBlue&lt;1&gt;/vgaBlue&lt;1&gt; is set but the tri state is not configured. 
</msg>

</messages>