hfrk_clib.c

Bootload 程序

    }
    if (size > nand_part[choice].size)
    {
        printf("file size is too large to the partition\n");
        return;
    }
    if (size > DWLD_POOL_SZ)
    {
        printf("file size is too large to the download pool\n");
        return;
    }

    dest = (INT8 *)DWLD_POOL_BASE_ADDR;

    printf("now please download file ...\n");

    ret_len = xmodem_receive(dest, size);
    if (!ret_len)
    {
        printf("failed to download file\n");
        return;
    }

    Delay(20); /* wait for a while, or the log below will not be print out */

    printf("file downloaded: addr = 0x%08x, len = %d\n", (UINT32)dest, size);

    if (OK != nand_write(choice, dest, size))
    {
        printf("failed to write to flash\n");
    }

    return;
}

void soft_reset(void)
{
    void (*func)(INT32 boot_type) = 0x0; /* virtual address */
    func(SOFT_RESET_FLAG);

    while (1) /* nothing */;
}

#ifdef __DBLDR_DEBUG__

#if 1 /* irq test functions */

static void __isr(void *param)
{
    printf("---> isr: IRQ_EINT0\n");
}

#endif

void test_field(void)
{
    #if 1

    #if 1 /* irq test functions */

    #include "hfrk_irq.h"
    hfrk_set_ext_irq_type(IRQ_EINT0, IRQ_TYPE_RISING_EDGE);
    hfrk_request_irq(IRQ_EINT0, __isr, NULL);
    hfrk_enable_irq(IRQ_EINT0);
    printf("---> irq enabled\n");

    #endif

    #else

    printf("NULL FUNCTION\n");

    #endif
}

#endif

/*****************************************************************************/

static INT32 delayLoopCount = 400;
void Delay(INT32 time)
{
    // time=0: adjust the Delay function by WatchDog timer.
    // time>0: the number of loop time
    // resolution of time is 100us.
    INT32 i,adjust=0;
    if(time==0)
    {
        time   = 200;
        adjust = 1;
        delayLoopCount = 400;
        //PCLK/1M,Watch-dog disable,1/64,interrupt disable,reset disable
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3);
        rWTDAT = 0xffff;                              //for first update
        rWTCNT = 0xffff;                              //resolution=64us @any PCLK
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3)|(1<<5); //Watch-dog timer start
    }
    for(;time>0;time--)
        for(i=0;i<delayLoopCount;i++);
    if(adjust==1)
    {
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3);   //Watch-dog timer stop
        i = 0xffff - rWTCNT;                     //1count->64us, 200*400 cycle runtime = 64*i us
        delayLoopCount = 8000000/(i*64);         //200*400:64*i=1*x:100 -> x=80000*100/(64*i)
    }
}

void ChangeClockDivider(INT32 hdivn, INT32 pdivn)
{
     // hdivn,pdivn FCLK:HCLK:PCLK
     //     0,0         1:1:1
     //     0,1         1:1:2
     //     1,0         1:2:2
     //     1,1         1:2:4
    rCLKDIVN = (hdivn<<1) | pdivn;

    if(hdivn)
        MMU_SetAsyncBusMode();
    else
        MMU_SetFastBusMode();
}

void ChangeMPllValue(INT32 mdiv, INT32 pdiv, INT32 sdiv)
{
    rMPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}

static void SetHclkPclk()
{
    if(sCLKDIVN&2)
        SYS_HCLK = SYS_FCLK>>1;
    else
        SYS_HCLK = SYS_FCLK;

    if(sCLKDIVN&1)
        SYS_PCLK = SYS_HCLK>>1;
    else
        SYS_PCLK = SYS_HCLK;
}

void SetClockDivider(INT32 hdivn, INT32 pdivn)
{
     // hdivn,pdivn FCLK:HCLK:PCLK
     //     0,0         1:1:1
     //     0,1         1:1:2
     //     1,0         1:2:2
     //     1,1         1:2:4
    if(SlowMode)
        return;

    hdivn &= 1;
    pdivn &= 1;
    sCLKDIVN = (hdivn<<1)|pdivn;
    rCLKDIVN = sCLKDIVN;

    if(hdivn)
        MMU_SetAsyncBusMode();
    else
        MMU_SetFastBusMode();

    SetHclkPclk();
}

UINT8 SetSysFclk(UINT32 val)
{
    UINT32 i, freq;
    UINT8 mdiv, pdiv, sdiv;

    if(SlowMode)
        return FALSE;

    mdiv = (val>>12)&0xff;
    pdiv = (val>>4)&0x3f;
    sdiv = val&0x3;

    i = (pdiv+2);
    while(sdiv--)
        i *= 2;

    freq = ((mdiv+8)*EXT_XTAL_FREQ)/i;
    if(freq>=(3*EXT_XTAL_FREQ)) {
        rMPLLCON = val;
        SYS_FCLK = freq;
        SetHclkPclk();
        if(os_timer_run) {
            os_timer_rld = SYS_PCLK/(8*4*Timer4Freq)-1;
            chg_os_timer = 1;
        }
        if(bios_timer_run) {
            bios_timer_rld = SYS_PCLK/(8*4*BIOS_TIMER_FREQ)-1;
            chg_bios_timer = 1;
        }
        return TRUE;
    }
    return FALSE;
}

void Port_Init(void)
{
    //CAUTION:Follow the configuration order for setting the ports.
    // 1) setting value(GPnDAT)
    // 2) setting control register  (GPnCON)
    // 3) configure pull-up resistor(GPnUP)

    //32bit data bus configuration
    //*** PORT A GROUP
    //Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
    //Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
    //Binary :  1     0      1  , 1   1   1    1   ,  1     1     1     1
    //Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0
    //Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
    //Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      0
    rGPACON = 0x5ffffe;

    //**** PORT B GROUP
    //Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0
    //Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
    //Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT
    //Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01
    rGPBCON = 0x044555;
    rGPBUP  = 0x7ff;     // The pull up function is disabled GPB[10:0]

    //*** PORT C GROUP
    //Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0
    //Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
    //Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10
    rGPCCON = 0xaaaaaaaa;
    rGPCUP  = 0xffff;     // The pull up function is disabled GPC[15:0]

    //*** PORT D GROUP
    //Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
    //Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8
    //Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10
    rGPDCON = 0xaaaaaaaa;
    rGPDUP  = 0xffff;     // The pull up function is disabled GPD[15:0]

    //*** PORT E GROUP
    //Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4
    //Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
    //Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,
    //-------------------------------------------------------------------------------------------------------
    //Ports  :  GPE3   GPE2  GPE1    GPE0
    //Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
    //Binary :  10     10  ,  10      10
    rGPECON = 0x5aaaaaaa;
    rGPEUP  = 0xffff;     // The pull up function is disabled GPE[15:0]

    //*** PORT F GROUP
    //Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
    //Signal : nLED_8 nLED_4  EINT5   EINT4  nIRQ_PCMCIA EINT2 KBDINT EINT0
    //Setting: Output Output                  EINT3    EINT2 EINT1  EINT0
    //Binary :  01      01 ,  10     10  ,     10       10  , 10     10
    rGPFCON = 0x5aaa;
    rGPFUP  = 0xff;     // The pull up function is disabled GPF[7:0]

    //*** PORT G GROUP
    //Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6
    //Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
    //Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
    //Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11
    //-----------------------------------------------------------------------------------------
    //Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0
    //Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
    //Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
    //Binary :     11         11   ,  10      11  ,  10        10
    rGPGCON = 0xff81ffba;   //GPG10 input,GPG9 input
    rGPGUP  = 0xffff;    // The pull up function is disabled GPG[15:0]

    //*** PORT H GROUP
    //Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0
    //Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
    //Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10
    rGPHCON = 0xfaaa;//0x2afaaa;
    rGPHUP  = 0x7ff;    // The pull up function is disabled GPH[10:0]

    //External interrupt will be falling edge triggered.
    rEXTINT0 = 0x22222222;    // EINT[7:0]
    rEXTINT1 = 0x22222224;    // EINT[15:8]
    rEXTINT2 = 0x22222222;    // EINT[23:16]
}

void led_disp(INT32 data)
{
    rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
}

void led_check_point(void)
{
    while (1)
    {
        led_disp(ALL_LEDS_OFF);
        Delay(5000);
        led_disp(ALL_LEDS_ON);
        Delay(5000);
    }
}

void HaltUndef(void)
{
    #if 0
    puts("Undefined instruction exception!!!\n");
    while(1);
    #else
    char *ptr = 0;
    int i;
    puts("Undefined instruction exception!!!\n");
    for (i = 0; i < 4; i++, ptr += 8)
    {
        printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",
            (*ptr) & 0xff,     (*(ptr + 1)) & 0xff, (*(ptr + 2)) & 0xff, (*(ptr + 3)) & 0xff,
            (*ptr + 4) & 0xff, (*(ptr + 5)) & 0xff, (*(ptr + 6)) & 0xff, (*(ptr + 7)) & 0xff);
    }
    #endif
}

void HaltSwi(void)
{
    #if 0
    puts("SWI exception!!!\n");
    while(1);
    #else
    char *ptr = 0;
    int i;
    puts("SWI exception!!!\n");
    for (i = 0; i < 4; i++, ptr += 8)
    {
        printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",
            (*ptr) & 0xff,     (*(ptr + 1)) & 0xff, (*(ptr + 2)) & 0xff, (*(ptr + 3)) & 0xff,
            (*ptr + 4) & 0xff, (*(ptr + 5)) & 0xff, (*(ptr + 6)) & 0xff, (*(ptr + 7)) & 0xff);
    }
    #endif
}

void HaltPabort(void)
{
    puts("Pabort exception!!!\n");
    while(1);
}

void HaltDabort(void)
{
    puts("Dabort exception!!!\n");
    while(1);
}

void Isr_Init(void)
{
    pISR_UNDEF  = (UINT32)HaltUndef;
    pISR_SWI    = (UINT32)HaltSwi;
    pISR_PABORT = (UINT32)HaltPabort;
    pISR_DABORT = (UINT32)HaltDabort;
    rINTMOD = 0x0;          /* All=IRQ mode */
    rINTMSK = BIT_ALLMSK;   /* All interrupt is masked, disabled. */
}

/*****************************************************************************/

void MMU_Init(void)
{
    INT32 i, j;

    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    MMU_DisableDCache();
    MMU_DisableICache();

    //If write-back is used,the DCache should be cleared.
    for(i = 0; i < 64; i++)
    {
        for(j = 0; j < 8; j++)
        {
            MMU_CleanInvalidateDCacheIndex((i << 26)|(j << 5));
        }
    }
    MMU_InvalidateICache();

    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache();
    #endif

    MMU_DisableMMU();
    MMU_InvalidateTLB();

    /* MMU_SetMTT(INT32 vaddrStart, INT32 vaddrEnd, INT32 paddrStart, INT32 attr); */

    /* !!! Important note, redirect IRQ vector to reset entry !!! */
    MMU_SetMTT(0x00000000, 0x00400000, RAM_HIGH_ADDR, RW_CB);  /* bank6-0: when no nor flash, must do it! */

    MMU_SetMTT(0x08000000, 0x10000000, 0x08000000, RW_NCNB);   /* bank1 */
    MMU_SetMTT(0x10000000, 0x18000000, 0x10000000, RW_NCNB);   /* bank2 */
    MMU_SetMTT(0x18000000, 0x20000000, 0x18000000, RW_NCNB);   /* bank3 */
    MMU_SetMTT(0x20000000, 0x28000000, 0x20000000, RW_NCNB);   /* bank4 */
    MMU_SetMTT(0x28000000, 0x30000000, 0x28000000, RW_NCNB);   /* bank5 */

    MMU_SetMTT(0x30000000, RAM_HIGH_ADDR, 0x30000000, RW_CB);  /* bank6-1 */
    MMU_SetMTT(RAM_HIGH_ADDR, RAM_HIGH_ADDR + _1M, 0x00000000, RW_CB); /* bank0: sram */
    MMU_SetMTT(RAM_HIGH_ADDR + _4M, 0x33f00000, RAM_HIGH_ADDR + _4M, RW_CB); /* bank6-2, mmu_tbl and stack left */
                                                                             /* assume dbldr'size is less than 4MB */

    MMU_SetMTT(0x38000000, 0x40000000, 0x38000000, RW_NCNB);   /* bank7 */

    MMU_SetMTT(0x40000000, 0x48000000, 0x40000000, RW_NCNB);   /* SFR */
    MMU_SetMTT(0x48000000, 0x5b000000, 0x48000000, RW_NCNB);   /* SFR */
    MMU_SetMTT(0x5b000000, 0xfff00000, 0x5b000000, RW_FAULT);  /* not used */

    MMU_SetTTBase(MMU_MAP_TBL_BASE_ADDR);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);

    //DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();

    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}

void MMU_SetMTT(INT32 vaddrStart, INT32 vaddrEnd, INT32 paddrStart, INT32 attr)
{
    UINT32 *pTT;
    INT32 i,nSec;
    pTT = (UINT32 *)MMU_MAP_TBL_BASE_ADDR + (vaddrStart >> 20);
    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
/*    for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20); */
    for (i = 0; i < nSec; i++) *pTT++ = attr | (((paddrStart >> 20) + i) << 20);
}