hfrk.h

Bootload 程序

#ifndef __HFRK_H__
#define __HFRK_H__

#include "dbldr_std.h"
#include "hfrk_cmd_line.h"

#define BOARD_NAME                   "hfrk dev board"

#define __LITTLE_ENDIAN__

#define POWER_ON_RESET_FLAG          (0x01)
#define POWER_OFF_RESET_FLAG         (0x02)
#define WDT_RESET_FLAG               (0x04)
#define SOFT_RESET_FLAG              (0x08)

#define RAM_BASE_ADDR                (0x30000000)
#define RAM_SZ                       (0x04000000) /* 64MB */

#define RAM_LOW_ADDR                 (0x30200000) /* why not (0x30080000) ? no reason. both are ok! :-) */
#define RAM_HIGH_ADDR                (0x33a00000)

#define DWLD_POOL_BASE_ADDR          (0x30400000)
#define DWLD_POOL_SZ                 (0x00800000) /* 8MB */

/* __bss_end ~ HEAP_END */
#define HEAP_END                     (0x33f00000) /* 1MB left */

/* 0x33ff3800 ~ 0x33ff8000 */
#define STACK_BASE_ADDR              (0x33ff8000)
#define STACK_MAX_SZ                 (0x00004800)

#define MMU_MAP_TBL_BASE_ADDR        (0x33ff9000)

/* exceptions map-table */
#define ISR_EXCEPTION_BASE_ADDR      (0x33ffff00)

#define ISR_RESET                    (ISR_EXCEPTION_BASE_ADDR + 0x0)
#define ISR_UNDEF                    (ISR_EXCEPTION_BASE_ADDR + 0x4)
#define ISR_SWI                      (ISR_EXCEPTION_BASE_ADDR + 0x8)
#define ISR_PABORT                   (ISR_EXCEPTION_BASE_ADDR + 0xc)
#define ISR_DABORT                   (ISR_EXCEPTION_BASE_ADDR + 0x10)
#define ISR_RESERVED                 (ISR_EXCEPTION_BASE_ADDR + 0x14)
#define ISR_IRQ                      (ISR_EXCEPTION_BASE_ADDR + 0x18)
#define ISR_FIQ                      (ISR_EXCEPTION_BASE_ADDR + 0x1c)

#if 0

#define ISR_IRQ_BASE_ADDR            (ISR_EXCEPTION_BASE_ADDR + 0x20)

#define ISR_EINT0                    (ISR_EXCEPTION_BASE_ADDR + 0x20)
#define ISR_EINT1                    (ISR_EXCEPTION_BASE_ADDR + 0x24)
#define ISR_EINT2                    (ISR_EXCEPTION_BASE_ADDR + 0x28)
#define ISR_EINT3                    (ISR_EXCEPTION_BASE_ADDR + 0x2c)
#define ISR_EINT4_7                  (ISR_EXCEPTION_BASE_ADDR + 0x30)
#define ISR_EINT8_23                 (ISR_EXCEPTION_BASE_ADDR + 0x34)
#define ISR_NOTUSED6                 (ISR_EXCEPTION_BASE_ADDR + 0x38)
#define ISR_BAT_FLT                  (ISR_EXCEPTION_BASE_ADDR + 0x3c)
#define ISR_TICK                     (ISR_EXCEPTION_BASE_ADDR + 0x40)
#define ISR_WDT                      (ISR_EXCEPTION_BASE_ADDR + 0x44)
#define ISR_TIMER0                   (ISR_EXCEPTION_BASE_ADDR + 0x48)
#define ISR_TIMER1                   (ISR_EXCEPTION_BASE_ADDR + 0x4c)
#define ISR_TIMER2                   (ISR_EXCEPTION_BASE_ADDR + 0x50)
#define ISR_TIMER3                   (ISR_EXCEPTION_BASE_ADDR + 0x54)
#define ISR_TIMER4                   (ISR_EXCEPTION_BASE_ADDR + 0x58)
#define ISR_UART2                    (ISR_EXCEPTION_BASE_ADDR + 0x5c)
#define ISR_LCD                      (ISR_EXCEPTION_BASE_ADDR + 0x60)
#define ISR_DMA0                     (ISR_EXCEPTION_BASE_ADDR + 0x64)
#define ISR_DMA1                     (ISR_EXCEPTION_BASE_ADDR + 0x68)
#define ISR_DMA2                     (ISR_EXCEPTION_BASE_ADDR + 0x6c)
#define ISR_DMA3                     (ISR_EXCEPTION_BASE_ADDR + 0x70)
#define ISR_SDI                      (ISR_EXCEPTION_BASE_ADDR + 0x74)
#define ISR_SPI0                     (ISR_EXCEPTION_BASE_ADDR + 0x78)
#define ISR_UART1                    (ISR_EXCEPTION_BASE_ADDR + 0x7c)
#define ISR_NOTUSED24                (ISR_EXCEPTION_BASE_ADDR + 0x80)
#define ISR_USBD                     (ISR_EXCEPTION_BASE_ADDR + 0x84)
#define ISR_USBH                     (ISR_EXCEPTION_BASE_ADDR + 0x88)
#define ISR_IIC                      (ISR_EXCEPTION_BASE_ADDR + 0x8c)
#define ISR_UART0                    (ISR_EXCEPTION_BASE_ADDR + 0x90)
#define ISR_SPI1                     (ISR_EXCEPTION_BASE_ADDR + 0x94)
#define ISR_RTC                      (ISR_EXCEPTION_BASE_ADDR + 0x98)
#define ISR_ADC                      (ISR_EXCEPTION_BASE_ADDR + 0x9c)

#define ISR_TBL_ENTRY_NUM            (0x20)

#endif

#define CORE_ENTRY                   (RAM_HIGH_ADDR + 0x1000)
#define KERNEL_ENTRY                 (RAM_LOW_ADDR)

/*****************************************************************************/

#define DEFAULT_UART_BAUD            (115200)
#define DEFAULT_UART_CHANNEL         (0)

#define FCLK                         (203000000)
#define HCLK                         (FCLK >> 1)
#define PCLK                         (HCLK >> 1)
#define UCLK                         (48000000)

#define FCLK_200M                    ((192<<12)|(4<<4)|1)
#define FCLK_203M                    ((161 << 12) | (3 << 4) | 1)

#define CS8900A_LOOP_BUF_SZ          (_1M)

/*****************************************************************************/

#undef  _HFRK_LINUX_2_4_
#define _HFRK_LINUX_2_6_

#define LINUX_PARAM_ADDR             (0x30000100) /* virtual address */

/*****************************************************************************/

#define SYS_CLK                      SYS_PCLK

#define BOARD_SPEC_INIT_ENTRY        hfrk_brd_init
#define INIT_STACK                   hfrk_init_stack
#define CP_CORE_TO_SDRAM             hfrk_cp_nand_to_sdram
#define CREATE_CORE_PARAM            hfrk_create_core_param

#define CORE_INIT                    hfrk_core_init /* init irq currently */
#define INIT_SDRAM                   hfrk_init_sdram
#define POST_INIT                    hfrk_post_init

#define MMU_ENABLE_ICACHE            MMU_EnableICache
#define MMU_DISABLE_ICACHE           MMU_DisableICache
#define MMU_ENABLE_DCACHE            MMU_EnableDCache
#define MMU_DISABLE_DCACHE           MMU_DisableDCache

#define LED_ON                       led_on
#define UART_PUTCH                   putch
#define UART_PUTS                    puts
#define UART_GETCH                   getch
#define UART_GETCH_TIMEOUT(pch, to)  getch_timeout((pch), (to))
#define UART_GETS                    gets
#define XMODEM_PUTC(x)               xmodem_putc((x))
#define XMODEM_AWAIT_KEY(x, y)       xmodem_await_key((x), (y))
#define AUTO_RUN_ROUTINE             run_prog(0x01) /* part_num = 1 */
#define DELAY(x)                     Delay((x))

#ifdef __ASM_LANGUAGE__

#ifdef __DBLDR_START__

.globl hfrk_brd_init
.globl hfrk_init_stack
.globl hfrk_cp_nand_to_sdram
.globl hfrk_create_core_param

#endif

#ifdef __DBLDR_CORE__

.globl SYS_PCLK

.globl hfrk_core_init
.globl hfrk_init_sdram
.globl hfrk_post_init
.globl putch
.globl puts
.globl getch
.globl getch_timeout
.globl gets
.globl xmodem_putc
.globl xmodem_await_key
.globl run_prog
.globl Delay

#endif

.globl led_on

#else /* !__ASM_LANGUAGE__ */

#ifdef __DBLDR_START__

void   hfrk_brd_init(void);
void   hfrk_init_stack(void);
void   hfrk_cp_nand_to_sdram(void);
UINT32 hfrk_create_core_param(void);

#endif

#ifdef __DBLDR_CORE__

extern UINT32 SYS_PCLK;

void   hfrk_init_sdram(void);
void   hfrk_core_init(void);
void   hfrk_post_init(void);
void   putch(INT8 ch);
INT32  puts(INT8 *str);
INT8   getch(void);
STATUS getch_timeout(INT8 *ch, INT32 ms);
INT32  gets(INT8 *str);
void   xmodem_putc(INT8 ch);
INT8   xmodem_await_key(UINT32 delay, INT32 *error_p);
void   run_prog(UINT32 part_num);
void   Delay(INT32 ms);

#endif

void led_on(void);

#endif /* __ASM_LANGUAGE__ */

#endif /* __HFRK_H__ */