2410addr.inc

Bootload 程序

#define EP3_DMA_TTC_M             0x52000253
#define EP3_DMA_TTC_H             0x52000257
#define EP4_DMA_CON               0x5200025b     /* EP4 DMA interface control */
#define EP4_DMA_UNIT              0x5200025f     /* EP4 DMA Tx unit counter */
#define EP4_DMA_FIFO              0x52000263     /* EP4 DMA Tx FIFO counter */
#define EP4_DMA_TTC_L             0x52000267     /* EP4 DMA total Tx counter */
#define EP4_DMA_TTC_M             0x5200026b
#define EP4_DMA_TTC_H             0x5200026f
#else /* Little Endian */
#define FUNC_ADDR_REG             0x52000140     /* Function address */
#define PWR_REG                   0x52000144     /* Power management */
#define EP_INT_REG                0x52000148     /* EP Interrupt pending and clear */
#define USB_INT_REG               0x52000158     /* USB Interrupt pending and clear */
#define EP_INT_EN_REG             0x5200015c     /* Interrupt enable */
#define USB_INT_EN_REG            0x5200016c
#define FRAME_NUM1_REG            0x52000170     /* Frame number lower byte */
#define FRAME_NUM2_REG            0x52000174     /* Frame number lower byte */
#define INDEX_REG                 0x52000178     /* Register index */
#define MAXP_REG                  0x52000180     /* Endpoint max packet */
#define EP0_CSR                   0x52000184     /* Endpoint 0 status */
#define IN_CSR1_REG               0x52000184     /* In endpoint control status */
#define IN_CSR2_REG               0x52000188
#define OUT_CSR1_REG              0x52000190     /* Out endpoint control status */
#define OUT_CSR2_REG              0x52000194
#define OUT_FIFO_CNT1_REG         0x52000198     /* Endpoint out write count */
#define OUT_FIFO_CNT2_REG         0x5200019c
#define EP0_FIFO                  0x520001c0     /* Endpoint 0 FIFO */
#define EP1_FIFO                  0x520001c4     /* Endpoint 1 FIFO */
#define EP2_FIFO                  0x520001c8     /* Endpoint 2 FIFO */
#define EP3_FIFO                  0x520001cc     /* Endpoint 3 FIFO */
#define EP4_FIFO                  0x520001d0     /* Endpoint 4 FIFO */
#define EP1_DMA_CON               0x52000200     /* EP1 DMA interface control */
#define EP1_DMA_UNIT              0x52000204     /* EP1 DMA Tx unit counter */
#define EP1_DMA_FIFO              0x52000208     /* EP1 DMA Tx FIFO counter */
#define EP1_DMA_TTC_L             0x5200020c     /* EP1 DMA total Tx counter */
#define EP1_DMA_TTC_M             0x52000210
#define EP1_DMA_TTC_H             0x52000214
#define EP2_DMA_CON               0x52000218     /* EP2 DMA interface control */
#define EP2_DMA_UNIT              0x5200021c     /* EP2 DMA Tx unit counter */
#define EP2_DMA_FIFO              0x52000220     /* EP2 DMA Tx FIFO counter */
#define EP2_DMA_TTC_L             0x52000224     /* EP2 DMA total Tx counter */
#define EP2_DMA_TTC_M             0x52000228
#define EP2_DMA_TTC_H             0x5200022c
#define EP3_DMA_CON               0x52000240     /* EP3 DMA interface control */
#define EP3_DMA_UNIT              0x52000244     /* EP3 DMA Tx unit counter */
#define EP3_DMA_FIFO              0x52000248     /* EP3 DMA Tx FIFO counter */
#define EP3_DMA_TTC_L             0x5200024c     /* EP3 DMA total Tx counter */
#define EP3_DMA_TTC_M             0x52000250
#define EP3_DMA_TTC_H             0x52000254
#define EP4_DMA_CON               0x52000258     /* EP4 DMA interface control */
#define EP4_DMA_UNIT              0x5200025c     /* EP4 DMA Tx unit counter */
#define EP4_DMA_FIFO              0x52000260     /* EP4 DMA Tx FIFO counter */
#define EP4_DMA_TTC_L             0x52000264     /* EP4 DMA total Tx counter */
#define EP4_DMA_TTC_M             0x52000268
#define EP4_DMA_TTC_H             0x5200026c
#endif /* __BIG_ENDIAN__ */

/*****************************************************************************/
/* WATCH DOG TIMER */
#define WTCON           0x53000000       /* Watch-dog timer mode */
#define WTDAT           0x53000004       /* Watch-dog timer data */
#define WTCNT           0x53000008       /* Eatch-dog timer count */

/*****************************************************************************/
/* IIC */
#define IICCON          0x54000000       /* IIC control */
#define IICSTAT         0x54000004       /* IIC status */
#define IICADD          0x54000008       /* IIC address */
#define IICDS           0x5400000c       /* IIC data shift */

/*****************************************************************************/
/* IIS */
#define IISCON          0x55000000       /* IIS Control */
#define IISMOD          0x55000004       /* IIS Mode */
#define IISPSR          0x55000008       /* IIS Prescaler */
#define IISFCON         0x5500000c       /* IIS FIFO control */

#ifdef __BIG_ENDIAN__
#define IISFIFO          0x55000012       /* IIS FIFO entry */
#else /* Little Endian */
#define IISFIFO          0x55000010       /* IIS FIFO entry */
#endif /* __BIG_ENDIAN__ */

/*****************************************************************************/
/* I/O PORT */
#define GPACON            0x56000000     /* Port A control */
#define GPADAT            0x56000004     /* Port A data */

#define GPBCON            0x56000010     /* Port B control */
#define GPBDAT            0x56000014     /* Port B data */
#define GPBUP             0x56000018     /* Pull-up control B */

#define GPCCON            0x56000020     /* Port C control */
#define GPCDAT            0x56000024     /* Port C data */
#define GPCUP             0x56000028     /* Pull-up control C */

#define GPDCON            0x56000030     /* Port D control */
#define GPDDAT            0x56000034     /* Port D data */
#define GPDUP             0x56000038     /* Pull-up control D */

#define GPECON            0x56000040     /* Port E control */
#define GPEDAT            0x56000044     /* Port E data */
#define GPEUP             0x56000048     /* Pull-up control E */

#define GPFCON            0x56000050     /* Port F control */
#define GPFDAT            0x56000054     /* Port F data */
#define GPFUP             0x56000058     /* Pull-up control F */

#define GPGCON            0x56000060     /* Port G control */
#define GPGDAT            0x56000064     /* Port G data */
#define GPGUP             0x56000068     /* Pull-up control G */

#define GPHCON            0x56000070     /* Port H control */
#define GPHDAT            0x56000074     /* Port H data */
#define GPHUP             0x56000078     /* Pull-up control H */

#define MISCCR            0x56000080     /* Miscellaneous control */
#define DCKCON            0x56000084     /* DCLK0/1 control */
#define EXTINT0           0x56000088     /* External interrupt control register 0 */
#define EXTINT1           0x5600008c     /* External interrupt control register 1 */
#define EXTINT2           0x56000090     /* External interrupt control register 2 */
#define EINTFLT0          0x56000094     /* Reserved */
#define EINTFLT1          0x56000098     /* Reserved */
#define EINTFLT2          0x5600009c     /* External interrupt filter control register 2 */
#define EINTFLT3          0x560000a0     /* External interrupt filter control register 3 */
#define EINTMASK          0x560000a4     /* External interrupt mask */
#define EINTPEND          0x560000a8     /* External interrupt pending */
#define GSTATUS0          0x560000ac     /* External pin status */
#define GSTATUS1          0x560000b0     /* Chip ID(0x32410000) */
#define GSTATUS2          0x560000b4     /* Reset type */
#define GSTATUS3          0x560000b8     /* Saved data0(32-bit) before entering POWER_OFF mode */
#define GSTATUS4          0x560000bc     /* Saved data1(32-bit) before entering POWER_OFF mode */

/*****************************************************************************/
/* RTC */
#ifdef __BIG_ENDIAN__
#define RTCCON          0x57000043       /* RTC control */
#define TICNT           0x57000047       /* Tick time count */
#define RTCALM          0x57000053       /* RTC alarm control */
#define ALMSEC          0x57000057       /* Alarm second */
#define ALMMIN          0x5700005b       /* Alarm minute */
#define ALMHOUR         0x5700005f       /* Alarm Hour */
#define ALMDAY          0x57000063       /* Alarm day */
#define ALMMON          0x57000067       /* Alarm month */
#define ALMYEAR         0x5700006b       /* Alarm year */
#define RTCRST          0x5700006f       /* RTC round reset */
#define BCDSEC          0x57000073       /* BCD second */
#define BCDMIN          0x57000077       /* BCD minute */
#define BCDHOUR         0x5700007b       /* BCD hour */
#define BCDDAY          0x5700007f       /* BCD day */
#define BCDDATE         0x57000083       /* BCD date */
#define BCDMON          0x57000087       /* BCD month */
#define BCDYEAR         0x5700008b       /* BCD year */
#else /* Little Endian */
#define RTCCON          0x57000040       /* RTC control */
#define TICNT           0x57000044       /* Tick time count */
#define RTCALM          0x57000050       /* RTC alarm control */
#define ALMSEC          0x57000054       /* Alarm second */
#define ALMMIN          0x57000058       /* Alarm minute */
#define ALMHOUR         0x5700005c       /* Alarm Hour */
#define ALMDAY          0x57000060       /* Alarm day */
#define ALMMON          0x57000064       /* Alarm month */
#define ALMYEAR         0x57000068       /* Alarm year */
#define RTCRST          0x5700006c       /* RTC round reset */
#define BCDSEC          0x57000070       /* BCD second */
#define BCDMIN          0x57000074       /* BCD minute */
#define BCDHOUR         0x57000078       /* BCD hour */
#define BCDDAY          0x5700007c       /* BCD day */
#define BCDDATE         0x57000080       /* BCD date */
#define BCDMON          0x57000084       /* BCD month */
#define BCDYEAR         0x57000088       /* BCD year */
#endif /* __BIG_ENDIAN__ */

/*****************************************************************************/
/* ADC */
#define ADCCON            0x58000000     /* ADC control */
#define ADCTSC            0x58000004     /* ADC touch screen control */
#define ADCDLY            0x58000008     /* ADC start or Interval Delay */
#define ADCDAT0           0x5800000c     /* ADC conversion data 0 */
#define ADCDAT1           0x58000010     /* ADC conversion data 1 */

/*****************************************************************************/
/* SPI */
#define SPCON0            0x59000000     /* SPI0 control */
#define SPSTA0            0x59000004     /* SPI0 status */
#define SPPIN0            0x59000008     /* SPI0 pin control */
#define SPPRE0            0x5900000c     /* SPI0 baud rate prescaler */
#define SPTDAT0           0x59000010     /* SPI0 Tx data */
#define SPRDAT0           0x59000014     /* SPI0 Rx data */

#define SPCON1            0x59000020     /* SPI1 control */
#define SPSTA1            0x59000024     /* SPI1 status */
#define SPPIN1            0x59000028     /* SPI1 pin control */
#define SPPRE1            0x5900002c     /* SPI1 baud rate prescaler */
#define SPTDAT1           0x59000030     /* SPI1 Tx data */
#define SPRDAT1           0x59000034     /* SPI1 Rx data */

/*****************************************************************************/
/* SD Interface */
#define SDICON            0x5a000000     /* SDI control */
#define SDIPRE            0x5a000000     /* SDI baud rate prescaler */
#define SDICmdArg         0x5a000000     /* SDI command argument */
#define SDICmdCon         0x5a000000     /* SDI command control */
#define SDICmdSta         0x5a000000     /* SDI command status */
#define SDIRSP0           0x5a000000     /* SDI response 0 */
#define SDIRSP1           0x5a000000     /* SDI response 1 */
#define SDIRSP2           0x5a000000     /* SDI response 2 */
#define SDIRSP3           0x5a000000     /* SDI response 3 */
#define SDIDTimer         0x5a000000     /* SDI data/busy timer */
#define SDIBSize          0x5a000000     /* SDI block size */
#define SDIDatCon         0x5a000000     /* SDI data control */
#define SDIDatCnt         0x5a000000     /* SDI data remain counter */
#define SDIDatSta         0x5a000000     /* SDI data status */
#define SDIFSTA           0x5a000000     /* SDI FIFO status */
#define SDIIntMsk         0x5a000000     /* SDI interrupt mask */
#ifdef __BIG_ENDIAN__
#define SDIDAT            0x5a00003f     /* SDI data */
#else /* Little Endian */
#define SDIDAT            0x5a00003c     /* SDI data */
#endif /* __BIG_ENDIAN__ */

#endif /* __ASM_LANGUAGE__ */

#endif /* __2410_ADDR_H__ */