2410addr.inc

Bootload 程序

#ifndef __2410_ADDR_H__
#define __2410_ADDR_H__

#ifdef __ASM_LANGUAGE__

#define __LITTLE_ENDIAN__

/*****************************************************************************/
/* Memory control */
#define BWSCON            0x48000000     /* Bus width & wait status */
#define BANKCON0          0x48000004     /* Boot ROM control */
#define BANKCON1          0x48000008     /* BANK1 control */
#define BANKCON2          0x4800000c     /* BANK2 cControl */
#define BANKCON3          0x48000010     /* BANK3 control */
#define BANKCON4          0x48000014     /* BANK4 control */
#define BANKCON5          0x48000018     /* BANK5 control */
#define BANKCON6          0x4800001c     /* BANK6 control */
#define BANKCON7          0x48000020     /* BANK7 control */
#define REFRESH           0x48000024     /* DRAM/SDRAM refresh */
#define BANKSIZE          0x48000028     /* Flexible Bank Size */
#define MRSRB6            0x4800002c     /* Mode register set for SDRAM */
#define MRSRB7            0x48000030     /* Mode register set for SDRAM */

/*****************************************************************************/
/* USB Host */

/*****************************************************************************/
/* INTERRUPT */
#define SRCPND             0x4a000000    /* Interrupt request status */
#define INTMOD             0x4a000004    /* Interrupt mode control */
#define INTMSK             0x4a000008    /* Interrupt mask control */
#define PRIORITY           0x4a00000a    /* IRQ priority control */
#define INTPND             0x4a000010    /* Interrupt request status */
#define INTOFFSET          0x4a000014    /* Interrupt request source offset */
#define SUSSRCPND          0x4a000018    /* Sub source pending */
#define INTSUBMSK          0x4a00001c    /* Interrupt sub mask */

/*****************************************************************************/
/* DMA */
#define DISRC0             0x4b000000    /* DMA 0 Initial source */
#define DISRCC0            0x4b000004    /* DMA 0 Initial source control */
#define DIDST0             0x4b000008    /* DMA 0 Initial Destination */
#define DIDSTC0            0x4b00000c    /* DMA 0 Initial Destination control */
#define DCON0              0x4b000010    /* DMA 0 Control */
#define DSTAT0             0x4b000014    /* DMA 0 Status */
#define DCSRC0             0x4b000018    /* DMA 0 Current source */
#define DCDST0             0x4b00001c    /* DMA 0 Current destination */
#define DMASKTRIG0         0x4b000020    /* DMA 0 Mask trigger */

#define DISRC1             0x4b000040    /* DMA 1 Initial source */
#define DISRCC1            0x4b000044    /* DMA 1 Initial source control */
#define DIDST1             0x4b000048    /* DMA 1 Initial Destination */
#define DIDSTC1            0x4b00004c    /* DMA 1 Initial Destination control */
#define DCON1              0x4b000050    /* DMA 1 Control */
#define DSTAT1             0x4b000054    /* DMA 1 Status */
#define DCSRC1             0x4b000058    /* DMA 1 Current source */
#define DCDST1             0x4b00005c    /* DMA 1 Current destination */
#define DMASKTRIG1         0x4b000060    /* DMA 1 Mask trigger */

#define DISRC2             0x4b000080    /* DMA 2 Initial source */
#define DISRCC2            0x4b000084    /* DMA 2 Initial source control */
#define DIDST2             0x4b000088    /* DMA 2 Initial Destination */
#define DIDSTC2            0x4b00008c    /* DMA 2 Initial Destination control */
#define DCON2              0x4b000090    /* DMA 2 Control */
#define DSTAT2             0x4b000094    /* DMA 2 Status */
#define DCSRC2             0x4b000098    /* DMA 2 Current source */
#define DCDST2             0x4b00009c    /* DMA 2 Current destination */
#define DMASKTRIG2         0x4b0000a0    /* DMA 2 Mask trigger */

#define DISRC3             0x4b0000c0    /* DMA 3 Initial source */
#define DISRCC3            0x4b0000c4    /* DMA 3 Initial source control */
#define DIDST3             0x4b0000c8    /* DMA 3 Initial Destination */
#define DIDSTC3            0x4b0000cc    /* DMA 3 Initial Destination control */
#define DCON3              0x4b0000d0    /* DMA 3 Control */
#define DSTAT3             0x4b0000d4    /* DMA 3 Status */
#define DCSRC3             0x4b0000d8    /* DMA 3 Current source */
#define DCDST3             0x4b0000dc    /* DMA 3 Current destination */
#define DMASKTRIG3         0x4b0000e0    /* DMA 3 Mask trigger */

/*****************************************************************************/
/* CLOCK & POWER MANAGEMENT */
#define LOCKTIME          0x4c000000     /* PLL lock time counter */
#define MPLLCON           0x4c000004     /* MPLL Control */
#define UPLLCON           0x4c000008     /* UPLL Control */
#define CLKCON            0x4c00000c     /* Clock generator control */
#define CLKSLOW           0x4c000010     /* Slow clock control */
#define CLKDIVN           0x4c000014     /* Clock divider control */

/*****************************************************************************/
/* LCD CONTROLLER */
#define LCDCON1           0x4d000000     /* LCD control 1 */
#define LCDCON2           0x4d000004     /* LCD control 2 */
#define LCDCON3           0x4d000008     /* LCD control 3 */
#define LCDCON4           0x4d00000c     /* LCD control 4 */
#define LCDCON5           0x4d000010     /* LCD control 5 */
#define LCDSADDR1         0x4d000014     /* STN/TFT Frame buffer start address 1 */
#define LCDSADDR2         0x4d000018     /* STN/TFT Frame buffer start address 2 */
#define LCDSADDR3         0x4d00001c     /* STN/TFT Virtual screen address set */
#define REDLUT            0x4d000020     /* STN Red lookup table */
#define GREENLUT          0x4d000024     /* STN Green lookup table */
#define BLUELUT           0x4d000028     /* STN Blue lookup table */
#define DITHMODE          0x4d00004c     /* STN Dithering mode */
#define TPAL              0x4d000050     /* TFT Temporary palette */
#define LCDINTPND         0x4d000054     /* LCD Interrupt pending */
#define LCDSRCPND         0x4d000058     /* LCD Interrupt source */
#define LCDINTMSK         0x4d00005c     /* LCD Interrupt mask */
#define LPCSEL            0x4d000060     /* LPC3600 Control */

/*****************************************************************************/
/* NAND flash */
#define NFCONF            0x4e000000     /* NAND Flash configuration */
#define NFCMD             0x4e000004     /* NADD Flash command */
#define NFADDR            0x4e000008     /* NAND Flash address */
#define NFDATA            0x4e00000c     /* NAND Flash data */
#define NFSTAT            0x4e000010     /* NAND Flash operation status */
#define NFECC             0x4e000014     /* NAND Flash ECC */

/*****************************************************************************/
/* UART */
#define ULCON0             0x50000000    /* UART 0 Line control */
#define UCON0              0x50000004    /* UART 0 Control */
#define UFCON0             0x50000008    /* UART 0 FIFO control */
#define UMCON0             0x5000000c    /* UART 0 Modem control */
#define UTRSTAT0           0x50000010    /* UART 0 Tx/Rx status */
#define UERSTAT0           0x50000014    /* UART 0 Rx error status */
#define UFSTAT0            0x50000018    /* UART 0 FIFO status */
#define UMSTAT0            0x5000001c    /* UART 0 Modem status */
#define UBRDIV0            0x50000028    /* UART 0 Baud rate divisor */

#define ULCON1             0x50004000    /* UART 1 Line control */
#define UCON1              0x50004004    /* UART 1 Control */
#define UFCON1             0x50004008    /* UART 1 FIFO control */
#define UMCON1             0x5000400c    /* UART 1 Modem control */
#define UTRSTAT1           0x50004010    /* UART 1 Tx/Rx status */
#define UERSTAT1           0x50004014    /* UART 1 Rx error status */
#define UFSTAT1            0x50004018    /* UART 1 FIFO status */
#define UMSTAT1            0x5000401c    /* UART 1 Modem status */
#define UBRDIV1            0x50004028    /* UART 1 Baud rate divisor */

#define ULCON2             0x50008000    /* UART 2 Line control */
#define UCON2              0x50008004    /* UART 2 Control */
#define UFCON2             0x50008008    /* UART 2 FIFO control */
#define UMCON2             0x5000800c    /* UART 2 Modem control */
#define UTRSTAT2           0x50008010    /* UART 2 Tx/Rx status */
#define UERSTAT2           0x50008014    /* UART 2 Rx error status */
#define UFSTAT2            0x50008018    /* UART 2 FIFO status */
#define UMSTAT2            0x5000801c    /* UART 2 Modem status */
#define UBRDIV2            0x50008028    /* UART 2 Baud rate divisor */

#ifdef __BIG_ENDIAN__
#define UTXH0              0x50000023    /* UART 0 Transmission Hold */
#define URXH0              0x50000027    /* UART 0 Receive buffer */
#define UTXH1              0x50004023    /* UART 1 Transmission Hold */
#define URXH1              0x50004027    /* UART 1 Receive buffer */
#define UTXH2              0x50008023    /* UART 2 Transmission Hold */
#define URXH2              0x50008027    /* UART 2 Receive buffer */
#else /* Little Endian */
#define UTXH0              0x50000020    /* UART 0 Transmission Hold */
#define URXH0              0x50000024    /* UART 0 Receive buffer */
#define UTXH1              0x50004020    /* UART 1 Transmission Hold */
#define URXH1              0x50004024    /* UART 1 Receive buffer */
#define UTXH2              0x50008020    /* UART 2 Transmission Hold */
#define URXH2              0x50008024    /* UART 2 Receive buffer */
#endif /* __BIG_ENDIAN__ */

/*****************************************************************************/
/* PWM TIMER */
#define TCFG0          0x51000000        /* Timer 0 configuration */
#define TCFG1          0x51000004        /* Timer 1 configuration */
#define TCON           0x51000008        /* Timer control */
#define TCNTB0         0x5100000c        /* Timer count buffer 0 */
#define TCMPB0         0x51000010        /* Timer compare buffer 0 */
#define TCNTO0         0x51000014        /* Timer count observation 0 */
#define TCNTB1         0x51000018        /* Timer count buffer 1 */
#define TCMPB1         0x5100001c        /* Timer compare buffer 1 */
#define TCNTO1         0x51000020        /* Timer count observation 1 */
#define TCNTB2         0x51000024        /* Timer count buffer 2 */
#define TCMPB2         0x51000028        /* Timer compare buffer 2 */
#define TCNTO2         0x5100002c        /* Timer count observation 2 */
#define TCNTB3         0x51000030        /* Timer count buffer 3 */
#define TCMPB3         0x51000034        /* Timer compare buffer 3 */
#define TCNTO3         0x51000038        /* Timer count observation 3 */
#define TCNTB4         0x5100003c        /* Timer count buffer 4 */
#define TCNTO4         0x51000040        /* Timer count observation 4 */

/*****************************************************************************/
/* USB DEVICE */
#ifdef __BIG_ENDIAN__
#define FUNC_ADDR_REG             0x52000143     /* Function address */
#define PWR_REG                   0x52000147     /* Power management */
#define EP_INT_REG                0x5200014b     /* EP Interrupt pending and clear */
#define USB_INT_REG               0x5200015b     /* USB Interrupt pending and clear */
#define EP_INT_EN_REG             0x5200015f     /* Interrupt enable */
#define USB_INT_EN_REG            0x5200016f
#define FRAME_NUM1_REG            0x52000173     /* Frame number lower byte */
#define FRAME_NUM2_REG            0x52000177     /* Frame number lower byte */
#define INDEX_REG                 0x5200017b     /* Register index */
#define MAXP_REG                  0x52000183     /* Endpoint max packet */
#define EP0_CSR                   0x52000187     /* Endpoint 0 status */
#define IN_CSR1_REG               0x52000187     /* In endpoint control status */
#define IN_CSR2_REG               0x5200018b
#define OUT_CSR1_REG              0x52000193     /* Out endpoint control status */
#define OUT_CSR2_REG              0x52000197
#define OUT_FIFO_CNT1_REG         0x5200019b     /* Endpoint out write count */
#define OUT_FIFO_CNT2_REG         0x5200019f
#define EP0_FIFO                  0x520001c3     /* Endpoint 0 FIFO */
#define EP1_FIFO                  0x520001c7     /* Endpoint 1 FIFO */
#define EP2_FIFO                  0x520001cb     /* Endpoint 2 FIFO */
#define EP3_FIFO                  0x520001cf     /* Endpoint 3 FIFO */
#define EP4_FIFO                  0x520001d3     /* Endpoint 4 FIFO */
#define EP1_DMA_CON               0x52000203     /* EP1 DMA interface control */
#define EP1_DMA_UNIT              0x52000207     /* EP1 DMA Tx unit counter */
#define EP1_DMA_FIFO              0x5200020b     /* EP1 DMA Tx FIFO counter */
#define EP1_DMA_TTC_L             0x5200020f     /* EP1 DMA total Tx counter */
#define EP1_DMA_TTC_M             0x52000213
#define EP1_DMA_TTC_H             0x52000217
#define EP2_DMA_CON               0x5200021b     /* EP2 DMA interface control */
#define EP2_DMA_UNIT              0x5200021f     /* EP2 DMA Tx unit counter */
#define EP2_DMA_FIFO              0x52000223     /* EP2 DMA Tx FIFO counter */
#define EP2_DMA_TTC_L             0x52000227     /* EP2 DMA total Tx counter */
#define EP2_DMA_TTC_M             0x5200022b
#define EP2_DMA_TTC_H             0x5200022f
#define EP3_DMA_CON               0x52000243     /* EP3 DMA interface control */
#define EP3_DMA_UNIT              0x52000247     /* EP3 DMA Tx unit counter */
#define EP3_DMA_FIFO              0x5200024b     /* EP3 DMA Tx FIFO counter */
#define EP3_DMA_TTC_L             0x5200024f     /* EP3 DMA total Tx counter */