📄 adb9t.s
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TTL ADB9T, ARM Development Board (ARM940T) Support
; ************************************************* */
; * * */
; * AMX 4-ARM Multitasking Kernel * */
; * ARM940T ADB Board Support * */
; * * */
; ************************************************* */
; */
; Copyright (c) 1999 */
; KADAK Products Ltd. */
; Vancouver, B.C., Canada */
; */
; All rights reserved. */
; */
; This document and source file contains CONFIDENTIAL INFORMATION */
; or trade secrets, or both, which are the property of KADAK */
; Products Ltd. This document and source file is subject to the */
; terms and conditions of the KADAK Products Ltd. Software License */
; Agreement which restricts the manner in which it may be used. */
; */
; Release Date: December 1, 1999 */
;
; INCLUDE CJZZZK.DEF ; Kernel assembler definitions
;
INCLUDE CJZZZK.DEF
;
; .eject # ------------------------------------------------------
; Support for the ARM Development Board (ARM940T)
;
; Devices on this board include:
;
; ST16C552 -
; Two 16 deep FIFO serial ports
; One parallel port
;
; One custom logic FPGA device -
; One interrupt controller (see ARM Reference Peripherals Spec)
; Two counter/timers (see ARM Reference Peripherals Spec)
;
; Memory map:
; 0x0A000000 Interrupt Controller base
; 0x0A800000 Counter/Timer base
;
; The ARM core supports one regular interrupt (IRQ) and one fast
; interrupt (FIQ). The ARM Development Board (ARM940T) supports multiple
; IRQ interrupts through an external interrupt controller.
;
; The IRQ interrupt controller uses a bit position for each different
; interrupt source and bit positions are defined for a software programmed
; interrupt, communication channels, timers, PC Card slots, and for
; the Advanced System Bus (ASB) and Advanced Peripheral Bus (APB).
; Bit 0 is unassigned in the IRQ controller so that it may share the
; same interrupt source as the FIQ controller.
; All IRQ interrupt source inputs are active HIGH and level sensitive.
; Any inversion or latching required to provide edge sensitivity must
; be provided at the generating source of the interrupt.
; A hardware priority scheme and automatic interrupt vectoring are not
; provided because these functions can be provided in software.
; A programmed interrupt register is provided to generate an interrupt
; under software control. This software interrupt is typically used
; to downgrade an FIQ interrupt to an IRQ interrupt.
;
; .eject # ------------------------------------------------------
; Set symbol KNEST to be non-zero if interrupt nesting is required.
; Interrupt nesting requires saving, setting and restoring of the
; interrupt disable mask for interrupt prioritization purposes.
;
; The state of KNEST must match the setting on the "Interrupts"
; property page in your Target Parameter File.
; If KNEST is 1, the IIP in this module will use 4 bytes of history storage.
;
;
; Definitions
;
KNEST EQU 1 ; Interrupt nesting is required
; ; (0/1 = no/yes)
ICBASE EQU 0x0A000000 ; Interrupt Controller base address
IRQSTAT EQU 0x000 ; IRQ status (read)
IRQRAWSTAT EQU 0x004 ; IRQ raw status (read)
IRQENABLE EQU 0x008 ; IRQ enable (read)
IRQENSET EQU 0x008 ; IRQ enable set (write)
IRQENCLR EQU 0x00C ; IRQ enable clear (write)
IRQSOFT EQU 0x010 ; Programmed IRQ interrupt (write)
FIQSTAT EQU 0x100 ; FIQ status (read)
FIQRAWSTAT EQU 0x104 ; FIQ raw status (read)
FIQENABLE EQU 0x108 ; FIQ enable (read)
FIQENSET EQU 0x108 ; FIQ enable set (write)
FIQENCLR EQU 0x10C ; FIQ enable clear (write)
FIQSOURCE EQU 0x114 ; FIQ interrupt source (read/write)
;
; ; IRQ status and enable bit masks
TMR1M EQU 0x00000010 ; Timer 1 interrupt bit mask
TMR2M EQU 0x00000020 ; Timer 2 interrupt bit mask
TMR1BN EQU 4 ; Timer 1 interrupt bit number
TMR2BN EQU 5 ; Timer 2 interrupt bit number
;
CTBASE EQU 0x0A800000 ; Counter/timer base address
CT1LOAD EQU 0x00 ; Timer 1 reload value (read/write)
CT1VALUE EQU 0x04 ; Timer 1 current value (read)
CT1CTRL EQU 0x08 ; Timer 1 control (read/write)
CT1CLEAR EQU 0x0C ; Timer 1 clear interrupt (write)
CT2LOAD EQU 0x20 ; Timer 2 reload value (read/write)
CT2VALUE EQU 0x24 ; Timer 2 current value (read)
CT2CTRL EQU 0x28 ; Timer 2 control (read/write)
CT2CLEAR EQU 0x2C ; Timer 2 clear interrupt (write)
;
; ; Counter/timer control bit masks
CTRLDIV1 EQU 0x00000000 ; Divide by 1 prescale
CTRLDIV16 EQU 0x00000040 ; Divide by 16 prescale
CTRLDIV256 EQU 0x00000080 ; Divide by 256 prescale
CTRLMPERIOD EQU 0x00000400 ; Periodic timer mode
CTRLENABLE EQU 0x00000800 ; Timer enable
;
; .eject # ------------------------------------------------------
; Instruction and Data Cache definitions
;
KCCCMD EQU 0xC0000000 ; Cache control command
; ; (see function chXXXcache)
; ; Select i-cache and d-cache
; ; Leave caches disabled
;
; Protection Unit definitions
;
PUAREADIS EQU 0x00000000 ; Disable memory area
PUAREAEN EQU 0x00000001 ; Enable memory area mask
;
PUSZ4KB EQU 0x00000016 ; Memory area size identifiers
PUSZ8KB EQU 0x00000018
PUSZ16KB EQU 0x0000001A
PUSZ32KB EQU 0x0000001C
PUSZ64KB EQU 0x0000001E
PUSZ128KB EQU 0x00000020
PUSZ256KB EQU 0x00000022
PUSZ512KB EQU 0x00000024
PUSZ1MB EQU 0x00000026
PUSZ2MB EQU 0x00000028
PUSZ4MB EQU 0x0000002A
PUSZ8MB EQU 0x0000002C
PUSZ16MB EQU 0x0000002E
PUSZ32MB EQU 0x00000030
PUSZ64MB EQU 0x00000032
PUSZ128MB EQU 0x00000034
PUSZ256MB EQU 0x00000036
PUSZ512MB EQU 0x00000038
PUSZ1GB EQU 0x0000003A
PUSZ2GB EQU 0x0000003C
PUSZ4GB EQU 0x0000003E
;
; The following definitions are used to setup the memory protection unit
; for use with the ARM Development Board (ARM940T).
; The memory areas and their attributes are:
;
; Area Name Base Address Size Access Cache Buffer
; 0 ARMUL 0x40000000 1 Gb Full Yes Yes
; 1 IO 0x0C000000 64 Mb Full No No
; 2 EXP 0x08000000 64 Mb Full No No
; 3 ROM 0x04000000 64 Mb Full Yes No
; 4 RAM 0x00000000 64 Mb Full Yes Yes
; 5 DRAM 0x03000000 16 Mb Full Yes Yes
; 6 SRAM 0x02000000 16 Mb Full Yes Yes
; 7 SSRAM 0x01000000 16 Mb Full Yes No
;
PUAREA0 EQU (0x40000000 :OR: PUSZ1GB :OR: PUAREAEN)
PUAREA1 EQU (0x0C000000 :OR: PUSZ64MB :OR: PUAREAEN)
PUAREA2 EQU (0x08000000 :OR: PUSZ64MB :OR: PUAREAEN)
PUAREA3 EQU (0x04000000 :OR: PUSZ64MB :OR: PUAREAEN)
PUAREA4 EQU (0x00000000 :OR: PUSZ64MB :OR: PUAREAEN)
PUAREA5 EQU (0x03000000 :OR: PUSZ16MB :OR: PUAREAEN)
PUAREA6 EQU (0x02000000 :OR: PUSZ16MB :OR: PUAREAEN)
PUAREA7 EQU (0x01000000 :OR: PUSZ16MB :OR: PUAREAEN)
;
PUCACHABLE EQU 0xF9 ; Cache areas 0,3-7
PUBUFFERABLE EQU 0x71 ; Write buffer areas 0,4-6
PUPROTECTION EQU 0xFFFF ; Full access to all areas
;
PUCTLMASK EQU 0x00000001 ; Protection unit enable mask (cr1)
;
;
; *****************
; * *
; * Start of ROM *
; * *
; *****************
;
;
; External references
;
IMPORT cjcfhwdelay ; I/O delay
IMPORT cjcfin8 ; Read I/O byte
IMPORT cjcfout8 ; Write I/O byte
IMPORT cjcfhwpcache ; Fetch cache parameters
IMPORT chv4rcache ; Cache Control Services
;
IF (:DEF:K_THUMB211)
AREA |ASM$$code|,CODE,READONLY,INTERWORK
ELSE
AREA |ASM$$code|,CODE,READONLY
ENDIF
;
; .eject # ------------------------------------------------------
; chbrdinit - Initialize the ARM Development Board (ARM940T)
;
; void CJ_CCPP chbrdinit(void) {}
;
; Note: This procedure programs the interrupt controller to
; disable ALL interrupt sources.
;
; Setup: None
; Return: a1..a4, ip, flags can be altered
; Interrupts are disabled and are then
; restored to their state upon entry.
;
EXPORT chbrdinit
chbrdinit EQU .
STMDB sp!,{v1,lr}
;
; Note: To support caching, the Protection Unit must be
; initialized and enabled.
; Note: If you want the caches and protection unit to be
; initialized, delete the following branch instruction.
; The cache initialization will invalidate and disable
; both the instruction and data caches.
; If the data cache is currently enabled,
; it will be flushed.
; The protection unit will be programmed as specified
; in the "Protection Unit definitions" section.
; The protection unit and write buffering will be enabled.
;
B CHBRDX
;
MOV a1,#0 ; a1 = 0 = NULL pointer
BL cjcfhwpcache ; Fetch cache parameters
;
; The following cache configuration parameters from the
; AMX Target Configuration Module have been loaded into registers:
; a2 = instruction cache total size (bytes)
; a3 = instruction cache line size (bytes)
; a4 = data cache total size (bytes)
; ip = data cache line size (bytes)
;
STMDB sp!,{ip} ; Push parameter on stack
LDR a1,=KCCCMD ; a1 = cache control command
;
MRS v1,CPSR ; v1 = current interrupt state
ORR lr,v1,#K_PSCIRQ:OR:K_PSCFIQ
MSR CPSR_c,lr ; -----disable interrupts
BL chv4rcache ; Initialize caches
;
ADR a2,CH940PUINIT
MRC p15,0,a3,c1,c0,0 ; Disable the memory protection unit
LDR a1,[a2],#4
AND a1,a1,a3
MCR p15,0,a1,c1,c0,0
;
LDR a1,[a2],#4 ; Define memory areas
MCR p15,0,a1,c6,c0,0
MCR p15,0,a1,c6,c0,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c1,0
MCR p15,0,a1,c6,c1,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c2,0
MCR p15,0,a1,c6,c2,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c3,0
MCR p15,0,a1,c6,c3,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c4,0
MCR p15,0,a1,c6,c4,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c5,0
MCR p15,0,a1,c6,c5,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c6,0
MCR p15,0,a1,c6,c6,1
LDR a1,[a2],#4
MCR p15,0,a1,c6,c7,0
MCR p15,0,a1,c6,c7,1
;
LDR a1,[a2],#4 ; Set caching attributes
MCR p15,0,a1,c2,c0,0
MCR p15,0,a1,c2,c0,1
LDR a1,[a2],#4 ; Set write buffering attributes
MCR p15,0,a1,c3,c0,0
LDR a1,[a2],#4 ; Set protection attributes
MCR p15,0,a1,c5,c0,0
MCR p15,0,a1,c5,c0,1
;
LDR a1,[a2],#4 ; Enable the memory protection unit
ORR a1,a1,a3
MCR p15,0,a1,c1,c0,0
;
MSR CPSR_c,v1 ; -----restore interrupts
ADD sp,sp,#4 ; Clean stack
;
CHBRDX MOV a4,#ICBASE ; Interrupt controller base address
MOV a3,#0xFFFFFFFF
STR a3,[a4,#IRQENCLR] ; Disable all interrupt sources
IF (K_THUMB<>0)
LDMIA sp!,{v1,lr}
BX lr
ELSE
LDMIA sp!,{v1,pc}
ENDIF
;
; Protection Unit Setup Constants Table
;
CH940PUINIT EQU .
; ; CP15 Reg. Purpose
DCD :NOT:PUCTLMASK ; AND c1,c0,0 Disable PU, Write Buffer
DCD PUAREA0 ; c6,c0,0+1 Memory Area #0
DCD PUAREA1 ; c6,c1,0+1 Memory Area #1
DCD PUAREA2 ; c6,c2,0+1 Memory Area #2
DCD PUAREA3 ; c6,c3,0+1 Memory Area #3
DCD PUAREA4 ; c6,c4,0+1 Memory Area #4
DCD PUAREA5 ; c6,c5,0+1 Memory Area #5
DCD PUAREA6 ; c6,c6,0+1 Memory Area #6
DCD PUAREA7 ; c6,c7,0+1 Memory Area #7
DCD PUCACHABLE ; c2,c0,0+1 Cache control bitmask
DCD PUBUFFERABLE ; c3,c0,0 Write buffer control bitmask
DCD PUPROTECTION ; c5,c0,0+1 Memory protection bitfields
DCD PUCTLMASK ; OR c1,c0,0 Enable PU, Write Buffer
;
; .eject # ------------------------------------------------------
; chclken/chclkdis - Enable/disable clock interrupts
;
; void CJ_CCPP chclken(int tmrnum) {}
; void CJ_CCPP chclkdis(int tmrnum) {}
;
; Setup: Interrupts must be disabled
; a1 = tmrnum (1 or 2)
; Return: a1..a4, ip, flags can be altered
; Interrupts are untouched
;
EXPORT chclken
chclken EQU .
SUB a4,a1,#1 ; Zero based timer number
CMP a4,#1
IF (K_THUMB<>0)
BXHI lr ; Return if timer number is invalid
ELSE
MOVHI pc,lr ; Return if timer number is invalid
ENDIF
;
MOV a4,#ICBASE ; Interrupt controller base address
MOV a3,a1,LSL #TMR1BN ; Timer bit of interest
STR a3,[a4,#IRQENSET] ; Enable timer
IF (K_THUMB<>0)
BX lr
ELSE
MOV pc,lr
ENDIF
;
EXPORT chclkdis
chclkdis EQU .
SUB a4,a1,#1 ; Zero based timer number
CMP a4,#1
IF (K_THUMB<>0)
BXHI lr ; Return if timer number is invalid
ELSE
MOVHI pc,lr ; Return if timer number is invalid
ENDIF
;
MOV a4,#ICBASE ; Interrupt controller base address
MOV a3,a1,LSL #TMR1BN ; Timer bit of interest
STR a3,[a4,#IRQENCLR] ; Disable timer
IF (K_THUMB<>0)
BX lr
ELSE
MOV pc,lr
ENDIF
;
; .eject # ------------------------------------------------------
; chadb7tirq - Interrupt Identification Procedure
; (for external IRQ vector)
;
; Setup: IRQ interrupts are disabled
; FIQ interrupts may be disabled
; sp = A(4 bytes of PIC state storage)
; lr[0] = device service entry/exit indicator
; = 0 if entering device service
; = 1 if exiting device service
; Return: If entering device service
; a1 = interrupt number (0..IRQMAX)
; = -2 if interrupt number cannot be derived
; a2..a4, ip, flags can be altered
; Interrupts are untouched
;
; If entering device service
; Do a linear search for highest priority pending IRQ interrupt
; (bit 0 of IRQ status is highest, bit 15 is lowest)
; If no pending IRQ requests are found
; Error: return device interrupt number = -2
; Else
; Save current IRQ mask
; Mask off all lower priority interrupts
; Return device interrupt number
; Else (device service exit)
; Restore IRQ mask from saved copy
;
;
EXPORT chadb7tirq
chadb7tirq EQU .
IF (KNEST<>0)
TST lr,#1
BNE KIRQ3 ; Device service exit
ENDIF
;
MOV a2,#ICBASE ; Interrupt controller base address
LDR a4,[a2,#IRQSTAT] ; a4 = IRQ status
MOV a1,#-1 ; Bit counter
MOVS a3,a4,LSL #16 ; Clear MS 16 bits, test result
BEQ KIRQ2 ; Source of interrupt is unknown
;
KIRQ1 MOVS a4,a4,LSR #1 ; Bit 0 is highest priority
ADD a1,a1,#1
BCC KIRQ1 ; Continue until set bit is found
;
IF (KNEST<>0)
LDR a4,[a2,#IRQENABLE] ; a4 = IRQ enable mask
ADR a3,KIRQ9 ; a3 = A(interrupt masks)
ADD a3,a3,a1,LSL #1 ; Use IRQ priority as word index
LDRH a3,[a3] ; a3 = priority interrupt mask
STRH a4,[sp] ; Save current enable mask
STR a3,[a2,#IRQENCLR] ; Disable all lower priority ints
ENDIF
MOV pc,lr ; Return; a1 = highest priority IRQ #
;
KIRQ2 MOV a1,#-2 ; Interrupt cause not found
MOV pc,lr
;
IF (KNEST<>0)
KIRQ3 LDRH a4,[sp] ; a4 = saved enable mask
MOV a2,#ICBASE ; Interrupt controller base address
STR a4,[a2,#IRQENSET] ; Restore interrupt enable status
BIC pc,lr,#1 ; Return
;
; Priority ordered interrupt disable masks
;
KIRQ9 DCW 0xFFFF ; Highest priority
DCW 0xFFFE
DCW 0xFFFC
DCW 0xFFF8
DCW 0xFFF0
DCW 0xFFE0
DCW 0xFFC0
DCW 0xFF80
DCW 0xFF00
DCW 0xFE00
DCW 0xFC00
DCW 0xF800
DCW 0xF000
DCW 0xE000
DCW 0xC000
DCW 0x8000 ; Lowest priority
ENDIF
;
;
; End of File
END
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