📄 embedded systems device driver development - page 5 of 9.htm
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<DIV class=ts5p2><SPAN class=ft0p5>IAR Aug 2000 </SPAN></DIV>
<DIV class=ts5p4><SPAN class=ft1p5>It is usually best to configure
low-level settings, such as the bus and interrupt controller,
</SPAN></DIV>
<DIV class=ts5p7><SPAN class=ft1p5>first as these may affect global
resources (in particular the number of available port </SPAN></DIV>
<DIV class=ts5p8><SPAN class=ft1p5>pins). </SPAN></DIV>
<DIV class=ts5p10><SPAN class=ft1p5></SPAN></DIV>
<DIV class=ts5p11><SPAN class=ft0p5></SPAN></DIV>
<DIV class=ts5p12><SPAN class=ft2p5>Figure 2: System setup of the bus
controller<SPAN class=ft3p5> </SPAN></SPAN></DIV>
<DIV class=ts5p14><SPAN class=ft1p5></SPAN></DIV>
<DIV class=ts5p15><SPAN class=ft4p5>Figure 2<SPAN class=ft1p5> shows
system configuration of the bus controller. External interfacing pins
(chip </SPAN></SPAN></DIV>
<DIV class=ts5p18><SPAN class=ft1p5>select 2) have been enabled, like some
other features (for instance memory expansion </SPAN></DIV>
<DIV class=ts5p19><SPAN class=ft1p5>mode). Other option pages can be used
to configure control pins, clocking, and the </SPAN></DIV>
<DIV class=ts5p20><SPAN class=ft1p5>watchdog timer. </SPAN></DIV>
<DIV class=ts5p23><SPAN class=ft1p5></SPAN></DIV>
<DIV class=ts5p24><SPAN class=ft0p5></SPAN></DIV>
<DIV class=ts5p25><SPAN class=ft2p5>Figure 3: Configuration of the
interrupt controller<SPAN class=ft3p5> </SPAN></SPAN></DIV>
<DIV class=ts5p27><SPAN class=ft1p5></SPAN></DIV>
<DIV class=ts5p28><SPAN class=ft4p5>Figure 3<SPAN class=ft1p5> shows the
dialog box for configuring the interrupt controller. INT1 and INT2
</SPAN></SPAN></DIV>
<DIV class=ts5p30><SPAN class=ft1p5>have been enabled with Both edges and
Rising edge triggering, respectively. For this </SPAN></DIV>
<DIV class=ts5p31><SPAN class=ft1p5>configuration, the code generator will
create an interrupt controller initialization function,
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