📄 embedded systems device driver development - page 6 of 9.htm
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<DIV class=ts6p1><SPAN class=ft0p6></SPAN></DIV>
<DIV class=ts6p2><SPAN class=ft0p6>IAR Aug 2000 </SPAN></DIV>
<DIV class=ts6p4><SPAN class=ft1p6>some support functions for priority
manipulation and interrupt handlers for the INT1 and </SPAN></DIV>
<DIV class=ts6p5><SPAN class=ft1p6>INT2 interrupts. </SPAN></DIV>
<DIV class=ts6p7><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p8><SPAN class=ft1p6>As the example above illustrates, also
very detailed target-dependent features can be </SPAN></DIV>
<DIV class=ts6p12><SPAN class=ft1p6>configured very easily using dialog
boxes. The graphic user interface prevents any </SPAN></DIV>
<DIV class=ts6p13><SPAN class=ft1p6>attempt to make illegal settings or
create resource conflicts, and gives a good overview </SPAN></DIV>
<DIV class=ts6p14><SPAN class=ft1p6>of the features available in the
selected chip and bus mode. </SPAN></DIV>
<DIV class=ts6p16><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p17><SPAN class=ft2p6>Peripheral module configuration
</SPAN></DIV>
<DIV class=ts6p20><SPAN class=ft1p6>All peripheral modules (such as UARTs,
DMA or CAN controllers, A/D or D/A converters, </SPAN></DIV>
<DIV class=ts6p21><SPAN class=ft1p6>etc) can be configured in the same
manner. <SPAN class=ft3p6>Figure 4</SPAN> shows how a serial </SPAN></DIV>
<DIV class=ts6p24><SPAN class=ft1p6>communications channel may be
configured in asynchronous mode. </SPAN></DIV>
<DIV class=ts6p26><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p27><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p28><SPAN class=ft4p6>Figure 4: Configuration of a UART
channel<SPAN class=ft5p6> </SPAN></SPAN></DIV>
<DIV class=ts6p31><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p32><SPAN class=ft1p6>Both transmit and receive interrupts
have been enabled, so the code generator will </SPAN></DIV>
<DIV class=ts6p33><SPAN class=ft1p6>create interrupt handlers and
implement interrupt-driven UART drivers using transmit </SPAN></DIV>
<DIV class=ts6p36><SPAN class=ft1p6>and receive buffers. The baud rate and
communications protocol have been configured </SPAN></DIV>
<DIV class=ts6p38><SPAN class=ft1p6>to 8 data bits, 1 stop bit, no parity,
and 19200 baud. </SPAN></DIV>
<DIV class=ts6p40><SPAN class=ft1p6></SPAN></DIV>
<DIV class=ts6p41><SPAN class=ft1p6>Other peripheral modules can be
configured in the same manner. </SPAN></DIV>
<DIV class=ts6p43><SPAN class=ft2p6>Code generation </SPAN></DIV>
<DIV class=ts6p45><SPAN class=ft1p6>Once the peripheral modules have been
configured satisfactorily, all SFR initialization </SPAN></DIV>
<DIV class=ts6p46><SPAN class=ft1p6>values are calculated and device
driver source code is generated automatically. </SPAN></DIV>
<DIV class=ts6p48><SPAN class=ft1p6>Dependent on the project settings, the
set of device driver functions or their internal </SPAN></DIV>
<DIV class=ts6p49><SPAN class=ft1p6>implementation may be different.
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