📄 vp.h
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#define VP_MASK_ADC2_EN 0x20 // [1]94 ADC 2 Enable
#define VP_MASK_SEL2 0x40 // [1]94 Analog MUX Select for ADC2
#define VP_MASK_GAIN2_SEL 0x80 // ???
// [1]97 $7.45.4 Luminance Process
#define VP_103_LUMA_PATH3 0x103
#define VP_MASK_CHT_EN 0x01 // [1]97 Chroma Trap Enable
#define VP_MASK_CHT_SEL 0x02 // [1]97 Chroma-Trap Control (Internal Test)
#define VP_MASK_PREF_EN 0x04 // [1]97 Luma Pre-Filter Enable (Y/C=OFF, CVBS=ON)
#define VP_MASK_YC_EN 0x08 // [1]95 Y/C Mode Enable
#define VP_MASK_VD_MON 0x80 // [1]20 Video Decoder status output select
// [1]96 $7.45.3 Color Standard Setting and detect
#define VP_104_VD_MODE 0x104 // [1]
#define VP_MASK_STD_SEL1 0x07 // [1]96 Color Standard Setup for Manual Setting and Semi-Auto on 50Hz
#define VP_MASK_STD_AUTO 0x08 // [1]96 Color Standard Detect
#define VP_MASK_FSEL 0x10 // [1]96 Manual 50/60Hz select
#define VP_MASK_AUFD 0x20 // [1]96 Auto 50/60Hz detect
#define VP_105_LUMA_ATTR 0x105 // [1]97
#define VP_MASK_BPASS_SEL 0x07 // [1]97 Band Pass Frequency Select
#define VP_MASK_COR_SEL 0x18 // [1]97 Coring circuit amplitude value
#define VP_MASK_APER_SEL 0x60 // [1]97 Aperture factor
#define VP_106_DVP_BRIGHTNESS 0x106 // [1]98 Brightness
#define VP_107_DVP_CONTRAST 0x107 // [1]98 Contrast
#define VP_108_DVP_BLACKLEVEL 0x108 // [1]98 Blacklevel
// [1]99 $7.45.5 Chroma Process
#define VP_109_DVP_SATURATION 0x109 // [1]99 Saturation Value
#define VP_10A_DVP_HUE 0x10A // [1]99 Chrominance HUE control
#define VP_10B_UGAIN 0x10B // [1]99 U Gain Value Adjustment
#define VP_10C_VGAIN 0x10C // [1]99 V Gain Value Adjustment
#define VP_10D_YDEL 0x10D // [1]98
#define VP_MASK_YDEL 0x0F // [1]98 Y Data Path Delay
#define VP_MASK_STD_SEL2 0x70 // [1]96 Color Standard Setup for Semi-Auto on 60Hz
#define VP_MASK_STD_MODE 0x80 // [1]96 Auto Color Standard Detect Mode Select
#define VP_10E_CHROMA_GAIN 0x10E // [1]99 Chroma Gain
#define VP_MASK_CHROMA_GAIN 0x7E
#define VP_MASK_CHROMA_GAIN_SEL 0x80
#define VP_10F110_GAIN_CTRL 0x10F // [1]99 Chroma Gain Reference value
#define VP_110_CHROMA_ATTR1 0x110 // [1]99
#define VP_MASK_GAIN_CTRL_MSB 0x01 // [1]99
#define VP_MASK_AUTO_KILL 0x02 // [1]99 Auto color kill from color detect
#define VP_MASK_CDV_SEL 0x04 // [1]99 TV / VCR Mode Select
#define VP_MASK_CCIR_EN 0x08 // [1]100 CCIR Mode
#define VP_MASK_GAIN_CTRL_SPEED 0x30 // [1]100 Auto Chroma Gain Loop Filter
#define VP_MASK_SECAM_INVERT 0x40 // [1]100 SECAM Invert Enable
#define VP_MASK_SXCR 0x80 // [1]100 SECAM Cross Color Reduction
#define VP_111_THRESHOLD_SECAM 0x111 // [1]100 Color Killer Threshold for SECAM
#define VP_112_THRESHOLD_QAM 0x112 // [1]100 Color Killer Threshold for PAL and NTSC
#define VP_113_SECAM_SENSITIVE 0x113 // [1]100 SECAM switch sensitive level
#define VP_114_PAL_SENSITIVE 0x114 // [1]100 PAL switch sensitive level
#define VP_115_CHROMA_BOUND 0x115 // [1]100
#define VP_MASK_LOWER_BOUND 0x0F // [1]100 Color Standard Detect Threshold 1
#define VP_MASK_UPPER_BOUND 0xF0 // [1]100 Color Standard Detect Threshold 2
#define VP_116_CHROMA_ATTR2 0x116
#define VP_MASK_CHROMA_LPPI1 0x03 // [1]100 Chroma Low Pass Filter Factor 1
#define VP_MASK_CHROMA_LPPI2 0x0C // [1]100 Chroma Low Pass Filter Factor 2
#define VP_MASK_SECS_SEL 0x10 // [1]100 SECAM freq. synchronize
#define VP_MASK_SQP_LPPI 0x60 // [1]100 Sub-Carrier Phase Detect factor 1
#define VP_MASK_SQP_SPUP 0x80 // [1]100 Sub-Carrier Phase Detect factor 2
#define VP_117_CHROMA_ATTR3 0x117 // [1]100
#define VP_MASK_STD_COUNT 0x3F // [1]96 Color Standard Detect Ready Threshold
#define VP_MASK_CHROMA_PHASE 0x40 // [1]100 Chroma Phase Detect Mode
#define VP_MASK_COMPENSATER_SEL 0x80 // [1]100 Sub-Carrier Lock Type
// [1]101 $7.45.6 Synchronization Process
#define VP_118_SYNC_IDEL 0x118 // [1]101 Horizontal increment delay
#define VP_119_SYNC_HSYS 0x119 // [1]101 Horizontal Sync Start
#define VP_11A_SYNC_HSYE 0x11A // [1]101 Horizontal Sync End
#define VP_11B_SYNC_HCS 0x11B // [1]101 Clamp Signal Start
#define VP_11C_SYNC_HCE 0x11C // [1]101 Clamp Signal End
#define VP_11D_SYNC_HSS 0x11D // [1]101 Horizontal Delay
#define VP_11E_BGPU_POINT 0x11E // [1]101 Burst Gap Start Point
#define VP_11F121_AGC_MASK_S 0x11F // [1]101 AGC Mask Start Point
#define VP_120121_AGC_MASK_E 0x120 // [1]101 AGC Mask End Point
#define VP_121_AGC_MASK 0x121 // [1]101 AGC Mask
#define VP_MASK_AGC_E_MSB 0x03
#define VP_MASK_AGC_S_MSB 0x30
#define VP_122_HLCK_THD 0x122 // [1]101 H-Lock Detect Threshold
#define VP_123_SLICER_THD 0x123 // [1]101 Sync-Slicer Threshold
#define VP_124_SYNC_ATTR1 0x124
#define VP_MASK_VNOISE_MODE 0x03 // [1]101 Vsync Detection Mode
#define VP_MASK_FIDT_THD 0xF0 // [1]101 50/60Hz Detect Threshold
#define VP_125_SYNC_ATTR2 0x125 // [1]101
#define VP_MASK_SYNC_LPADJ 0x03 // [1]101 Low Pass Filter Margin Value
#define VP_MASK_SYNC_PDGAIN 0x0C // [1]101 Phase Detection Margin Value
#define VP_MASK_SYNC_LPLMT 0x10 // [1]101 Low pass filter trace value
#define VP_MASK_SYNC_HPLL 0x20 // [1]101 HPLL Mode Enable
#define VP_MASK_VTRC 0x80 // [1]101 VCR Mode Enable
// [1]104 $7.45.8 Analog AGC Control
#define VP_126128_GAIN1_VALUE 0x126
#define VP_127128_GAIN2_VALUE 0x127
#define VP_128_GAIN_ATTR 0x128
#define VP_MASK_GAIN1_VALUE_MSB 0x01 // [1]104 Fixed Gain Value for ADC1
#define VP_MASK_FIXGAIN1_EN 0x02 // [1]104 Auto Gain Control Enable fro ADC1
#define VP_MASK_GAIN2_VALUE_MSB 0x10 // [1]104 Fixed Gain Value for ADC2
#define VP_MASK_FIXGAIN2_EN 0x20 // [1]104 Auto Gain Control Enable fro ADC2
#define VP_MASK_GAIN_HOLD 0x80 // [1]104 Auto Gain Control Hold
// [1]105 $7.45.9 Analog Clamp Control
#define VP_129_AAGC_ATTR 0x129
#define VP_MASK_GAIN_SEL 0x01 // [1]104 Gain Source Select
#define VP_MASK_GAIN_HLCK 0x02 // [1]104 Fixed Gain Enable on HLCK
#define VP_MASK_AAGC_VSMODE 0x04 // [1]105 Analog Clamp and Gain Vsync Mode
#define VP_MASK_MACROVISION_EN 0x08 // [1]105 Analog Clamp and GAIN Disable on VSYNC
#define VP_MASK_GAIN_THB 0xF0 // [1]104 AGC Bottom Threshold Value
#define VP_12A_ACLAMP_LEVEL 0x12A // [1]105 Analog Clamp Level
#define VP_12B_ACLAMP_ATTR 0x12B // [1]105
#define VP_MASK_ACLAMP1_EN 0x01
#define VP_MASK_ACLAMP1_MODE 0x02
#define VP_MASK_ACLAMP1_SPEED 0x0C
#define VP_MASK_ACLAMP2_EN 0x10
#define VP_MASK_ACLAMP2_MODE 0x20
#define VP_MASK_ACLAMP2_SPEED 0xC0
// [1]106 $7.45.10 Digital AGC and Clamp Control
#define VP_12C12E_DGAIN1_VALUE 0x12C // [1]106
#define VP_12D12E_DGAIN2_VALUE 0x12D // [1]106
#define VP_12E_DAGC_ATTR 0x12E // [1]106
#define VP_MASK_DGAIN1_VALUE_MSB 0x01
#define VP_MASK_FIXDGAIN1_EN 0x02 // [1]106 Digital Fixed Gain Control Enable for ADC1
#define VP_MASK_DGAIN1_SEL 0x04 // [1]106 Gain source select for ADC1
#define VP_MASK_DGAIN1_AUTO 0x08 // [1]106 Digital AGC1 and Clamp Auto Enable
#define VP_MASK_DGAIN2_VALUE_MSB 0x10
#define VP_MASK_FIXDGAIN2_EN 0x20 // [1]106 Digital Fixed Gain Control Enable for ADC2
#define VP_MASK_DGAIN2_SEL 0x40 // [1]106 Gain source select for ADC2
#define VP_MASK_DGAIN2_AUTO 0x80 // [1]107 Digital AGC2 and Clamp Auto Enable
#define VP_12F_DCLAMP_ATTR1 0x12F // [1]106
#define VP_MASK_DCLAMP1_EN 0x01
#define VP_MASK_DCLAMP1_HOLD 0x02
#define VP_MASK_DCLAMP1_TYPE 0x04 // [1]106 Clamp Level for ADC1 Channel
#define VP_MASK_DCLAMP1_MODE 0x08 // [1]105 Clamp 1 Type
#define VP_MASK_DCLAMP2_EN 0x10 // [1]107
#define VP_MASK_DCLAMP2_HOLD 0x20
#define VP_MASK_DCLAMP2_TYPE 0x40 // [1]107 Clamp Level for ADC2 Channel
#define VP_MASK_DCLAMP2_MODE 0x80 // [1]105 Clamp 2 Type
#define VP_130_DCLAMP_ATTR2 0x130
#define VP_MASK_CLAMP_SPEED 0x0F // [1]107 Digital Clamp Speed
#define VP_MASK_DAGC_VSMODE 0x10 // [1]107 Digital AGC VSYNC Mode
#define VP_MASK_HCLK_SEL 0xC0 // [1]13 Video Decoder Lock source for interrupt select
#define VP_131_DCLAMP_VALUE 0x131 // [1]107
// [1]110 $7.45.13 Comb Filter Control
#define VP_132_COMB_NRTH 0x132 // [1]110 Noise Reduce Threshold for 2D Comb Filter
#define VP_133_COMB_THD 0x133 // [1]110 Threshold for Filter Selection
#define VP_134_COMB_ATTR 0x134 // [1]110 COMB Attribute
#define VP_MASK_COMB_THD_MSB 0x0F // Threshold for Filter Selection
#define VP_MASK_COMB_YDEL 0x10 // Y Data Path Delay
#define VP_MASK_COMB_SEL 0x20 // Comb Filter Select
#define VP_MASK_FREQ_SEL 0x40 // Frequency Select
#define VP_MASK_COMB_EN 0x80 // Adaptive Comb Filter Enable
#define VP_135_HS_DLY 0x135 // [1]110 COMB Attribute
#define VP_MASK_HS_DELAY 0x07 // [1]110 HSYNC Delay
#define VP_MASK_HS_MASK_EN 0x10 // [1]110 HSYNC Mask Enable
#define VP_MASK_VS_MASK_EN 0x20 // [1]110 VSYNC Mask Enable
#define VP_MASK_SQP_LMT 0x40 // [1]100 Sub-Carrier Phase Detect factor 3
// [1]108 $7.45.11 ADC Control
#define VP_136_AFE_CTRL 0x136
#define VP_MASK_SAD10 0x01 // ADC1 Switch 1 Enable
#define VP_MASK_SAD11 0x02 // ADC1 Switch 2 Enable
#define VP_MASK_AMUX1 0x04 // Bypass PGA
#define VP_MASK_SAD20 0x10 // ADC2 Switch 1 Enable
#define VP_MASK_SAD21 0x20 // ADC2 Switch 2 Enable
#define VP_MASK_AMUX2 0x40 // Bypass PGA
#define VP_MASK_ADCTEST 0x80 // ADC Test Mode Enable
// [1]109 $7.45.12 AFE PLL Clock Control
#define VP_137_AFE_PLL 0x137
#define VP_MASK_INV_CLK 0x01 // [1]109 Clock Polarity
#define VP_MASK_DVT_PLL 0x02 // [1]109 Source Select
#define VP_MASK_ADCCLK_INV 0x04 // [1]108 ADC Clock Polarity
#define VP_MASK_ADCCLK_SEL 0x08 // [1]108 CLK Source Select
#define VP_MASK_RMUX 0x10 // [1]109 Reference Clock Select
#define VP_MASK_PMUX 0x20 // [1]109 PLL Clock phase s⌨️ 快捷键说明
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