📄 vp.h
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#define VP_MASK_TIMER0_EN 0x04 // [1]77 Timer0 Enable
#define VP_MASK_TIMER0_MODE 0x08 // [1]77 Timer0 Count Mode
#define VP_0BC_TIMER1_COUNT 0x0BC // [1]77 Timer1 Count value
#define VP_0BD_TIMER1_ATTR 0x0BD // [1]77 Timer1 Attribute
#define VP_MASK_TIMER1_BASE_MODE 0x03 // [1]77 Timer1 Count Base
#define VP_MASK_TIMER1_EN 0x04 // [1]77 Timer1 Enable
#define VP_MASK_TIMER1_MODE 0x08 // [1]77 Timer1 Count Mode
// [1]79 $7.37 GPI and KEY Function
#define VP_0C0_DB 0x0C0 // [1]79
#define VP_MASK_KEY_SEL 0x07 // [1]79 Input pinsselect
#define VP_MASK_KEY_DB 0x18 // [1]79 GPI debounce setup
#define VP_MASK_POWER_DB 0xE0 // [1]89 Feedback debounce setup
#define VP_0C1_KEY_ACK 0x0C1 // [1]79 GPI read back status
#define VP_0C2_KEY_STATUS 0x0C2 // [1]79 Real time GPI status
#define VP_0C3_KEY_POL 0x0C3 // [1]79 GPI Polarity
#define VP_0C4_KEY_TYPE_1234 0x0C4 // [1]79 GPI[4:1] Type setup
#define VP_MASK_KEY_TYPE_1 0x03
#define VP_MASK_KEY_TYPE_2 0x0C
#define VP_MASK_KEY_TYPE_3 0x30
#define VP_MASK_KEY_TYPE_4 0xC0
#define VP_0C5_KEY_TYPE_5678 0x0C5 // [1]79 GPI[8:5] Type setup
#define VP_MASK_KEY_TYPE_5 0x03
#define VP_MASK_KEY_TYPE_6 0x0C
#define VP_MASK_KEY_TYPE_7 0x30
#define VP_MASK_KEY_TYPE_8 0xC0
// [1]38 $7.16 External Pin Setup
#define VP_0C8_EXT_ATTR1 0x0C8 // [1]38 EXT Attribute 1
#define VP_MASK_STH_M0 0x01 // STH Output Selection
#define VP_MASK_STV_M0 0x02 // STV Output Selection
#define VP_MASK_RL_M0 0x04 // TCON R/L
#define VP_MASK_UD_M0 0x08 // TCON U/D
#define VP_MASK_Q2H_M0 0x10 // Q2H Output Polarity
#define VP_MASK_STH_M1 0x20 // STH Output Selection
#define VP_MASK_STV_M1 0x40 // STV Output Selection
#define VP_MASK_RL_M1 0x80 // TCON R/L
#define VP_0C9_EXT_ATTR2 0x0C9 // [1]38 EXT Attribute 2
#define VP_MASK_UD_M1 0x01 // TCON U/D
#define VP_MASK_Q2H_M1 0x02 // Q2H Output Polarity
#define VP_MASK_STH_M3 0x04 // STH Output Selection
#define VP_MASK_STV_M3 0x08 // STV Output Selection
#define VP_MASK_RL_M3 0x10 // TCON R/L
#define VP_MASK_UD_M3 0x20 // TCON U/D
#define VP_MASK_Q2H_M3 0x40 // Q2H Output Polarity
#define VP_MASK_EXTPIN 0x80 //
// [1]81 $7.38 Auto Detection
#define VP_0CB_MODECHG_MRG 0x0CB // Auto Detection VS Threshold
#define VP_MASK_MODECHG_MRG 0x0F // [1]81 VS maxium threshold
#define VP_MASK_MCU_DEBUG 0x80 // ???
// [1]82 $7.39 EEPROM Setup
// [1]83 $7.40 Serial Peripheral Interface (SPI)
#define VP_0CC_SPI_ATTR 0x0CC
#define VP_MASK_SERIAL_CKEN_SEL 0x07 // [1]82 EEPROM Read/Write Speed
#define VP_MASK_SPI_EN 0x08 // [1]83 SPI Enable
#define VP_MASK_SPI_SPEED 0x30 // [1]83 SPI Speed Select
#define VP_MASK_SPI_MODE 0xC0 // [1]83 SPI Mode Select
#define VP_0CD_I2C_SLAVE 0x0CD // [1]82 Script Control I2C Command Slave Setup
// [1]84 $7.41 Power Sequence Control
#define VP_0CF0D5_P1_HSYNC 0x0CF // [1]84 Phase 1 Delay with HS
#define VP_0D00D5_P2_HSYNC 0x0D0 // [1]84 Phase 2 Delay with HS
#define VP_0D10D5_P3_HSYNC 0x0D1 // [1]84 Phase 3 Delay with HS
#define VP_0D20D5_P4_HSYNC 0x0D2 // [1]84 Phase 4 Delay with HS
#define VP_0D30D5_P5_HSYNC 0x0D3 // [1]84 Phase 5 Delay with HS
#define VP_0D40D5_P6_HSYNC 0x0D4 // [1]84 Phase 6 Delay with HS
#define VP_0D5_POWER_HSYNC 0x0D5 // [1]84 Phase Delay with HS
#define VP_MASK_P1_HSYNC_MSB 0x01
#define VP_MASK_P2_HSYNC_MSB 0x02
#define VP_MASK_P3_HSYNC_MSB 0x04
#define VP_MASK_P4_HSYNC_MSB 0x08
#define VP_MASK_P5_HSYNC_MSB 0x10
#define VP_MASK_P6_HSYNC_MSB 0x20
#define VP_MASK_DATA_CTRL 0x40 // [1]84 Data Output Control enable
#define VP_MASK_POWER_EN 0x80 // [1]84 Power Sequence Function enable
#define VP_0D6_P12_VSYNC 0x0D6 // [1]84 Phase 1 & 2 Delay with VS
#define VP_MASK_P1_VSYNC 0x0F
#define VP_MASK_P2_VSYNC 0xF0
#define VP_0D7_P34_VSYNC 0x0D7 // [1]84 Phase 3 & 4 Delay with VS
#define VP_MASK_P3_VSYNC 0x0F
#define VP_MASK_P4_VSYNC 0xF0
#define VP_0D8_P56_VSYNC 0x0D8 // [1]84 Phase 5 & 6 Delay with VS
#define VP_MASK_P5_VSYNC 0x0F
#define VP_MASK_P6_VSYNC 0xF0
#define VP_0D9_POWER_ATTR 0x0D9 // [1]84 Phase Polarity
#define VP_MASK_P1_POL 0x01
#define VP_MASK_P2_POL 0x02
#define VP_MASK_P3_POL 0x04
#define VP_MASK_P4_POL 0x08
#define VP_MASK_DATA_UP 0x70 // [1]84 Data Control Phase select
#define VP_0DA_POWER_SEL 0x0DA // [1]84 Power Sequence output control
#define VP_0DB_P56_ATTR 0x0DB // [1]84 Power phase 5 & 6 output select
#define VP_MASK_P5 0x07 // [1]84
#define VP_MASK_P5_POL 0x08
#define VP_MASK_P6 0x70 // [1]85
#define VP_MASK_P6_POL 0x80
// [1]86 $7.42 PWM Function
// [1]86 PWM1 Function
#define VP_0DE0E1_SYNC_DELAY 0x0DE // [1]86 Synchronize delay time
#define VP_0DF0E1_PWM1_REF 0x0DF // [1]86 PWM1/PWM3 Reference Frequency[7:0]
#define VP_0E00E1_PWM1_FREQ 0x0E0 // [1]86 PWM1 Frequency[7:0]
#define VP_0E1_PWM1_ATTR 0x0E1 // [1]86 PWM1 Attribute
#define VP_MASK_PWM1_REF_MSB 0x03 // [1]86 PWM1/PWM3 Reference Frequency[9:8]
#define VP_MASK_PWM1_FREQ_MSB 0x10 // [1]86 PWM1 Frequency[8]
#define VP_MASK_SYNC_DELAY_MSB 0x40 // [1]86
#define VP_0E20E3_PWM1_DUTY 0x0E2 // [1]86 PWM1 Duty[8:0]
#define VP_0E3_PWM1_DUTY_MSB 0x0E3 // [1]86
// [1]86 PWM2 Function
#define VP_0E40E7_PWM2_REF 0x0E4 // [1]86 PWM2 Reference Frequency[7:0]
#define VP_0E50E7_PWM2_FREQ 0x0E5 // [1]86 PWM2 Frequency[7:0]
#define VP_0E6_PWM_SYNC_DELAY 0x0E6 // [1]86 PWM2 delay phase to PWM1
#define VP_0E7_PWM2_ATTR 0x0E7 // [1]86 PWM2 Attribute
#define VP_MASK_PWM2_REF_MSB 0x03 // [1]86 PWM2 Reference Frequency
#define VP_MASK_PWM2_FREQ_MSB 0x10 // [1]86 PWM2 Frequency
#define VP_MASK_PWM_SYNC_DELAY_MSB 0x20 // [1]86 PWM2
#define VP_0E80E9_PWM2_DUTY 0x0E8 // [1]86 PWM2 Duty[8:0]
#define VP_0EA_PWM12_ATTR 0x0EA // [1]86 PWM12 Attribute
#define VP_MASK_PWM1_SYNC 0x01 // [1]86 PWM1 Synchronized wiht VSYNC
#define VP_MASK_PWM1_POL 0x02 // [1]86 PWM1 Output Polarity
#define VP_MASK_PWM1_SEL 0x04 // [1]86 PWM1 Output select
#define VP_MASK_SYNC_OHS 0x08 // [1]86 PWM1 Output select
#define VP_MASK_PWM2_SYNC 0x10 // [1]86 PWM2 Synchronized wiht VSYNC
#define VP_MASK_PWM2_POL 0x20 // [1]86 PWM2 Output Polarity
#define VP_MASK_PWM2_SYNC_EN 0x40 // [1]86 PWM2 PWM2 synchronized with PWM1
#define VP_MASK_PWM2_SEL 0x80 // [1]87 PWM2 Output select
// [1]88 $7.43 Feedback PWM Control
// [1]88 PWM3 Function
#define VP_0EB_PWM3_FREQ 0x0EB // [1]88 PWM3 Frequency[7:0]
#define VP_0EC_PWM3_DUTY 0x0EC // [1]88 PWM3 Duty[7:0]
// [1]76 PWM4 Function
#define VP_0ED_PWM4_FREQ 0x0ED // [1]88 PWM4 Frequency[7:0]
#define VP_0EE_PWM4_DUTY 0x0EE // [1]88 PWM4 Duty[7:0]
#define VP_0EF_FB_LOW 0x0EF // [1]88 Feedback tracer low limit
#define VP_0F0_FB_HIGH 0x0F0 // [1]88 Feedback tracer high limit
#define VP_0F1_PWM34_ATTR 0x0F1 // [1]88 PWM34 Attribute
#define VP_MASK_PWM3_POL 0x01 // [1]88 PWM3 Output Polarity
#define VP_MASK_PWM3_FB 0x02 // [1]88 PWM3 Feedback Enable
#define VP_MASK_PWM3_SEL 0x04 // [1]88 PWM3 Synchronization Source
#define VP_MASK_PWM3_SYNC 0x08 // [1]88 PWM3 Mode
#define VP_MASK_PWM4_POL 0x10 // [1]88 PWM4 Output Polarity
#define VP_MASK_PWM4_FB 0x20 // [1]88 PWM4 Feedback Enable
#define VP_MASK_PWM4_SEL 0x40 // [1]88 PWM4 Synchronization Source
#define VP_MASK_PWM4_SYNC 0x80 // [1]88 PWM4 Mode
// [1]90 $7.44 IR Decoder Function
#define VP_0F5_IR_DATA_BAR 0x0F5 // [1]90 IR /Data
#define VP_0F6_IR_CODE_BAR 0x0F6 // [1]90 IR /Code
#define VP_0F7_IR_DATA 0x0F7 // [1]90 IR Data
#define VP_0F8_IR_CODE 0x0F8 // [1]90 IR Code
#define VP_0F9_IR_UDCC_BAR 0x0F9 // [1]90 User Defined Customer /Code
#define VP_0FA_IR_UDCC 0x0FA // [1]90 User Defined Customer Code
#define VP_0F90FA_IR_UDCC 0x0F9 // [1]90 User Defined Customer Code
#define VP_0FB_IR_ATTR 0x0FB // [1]90 IR Attribute
#define VP_MASK_IR_EN 0x01 // [1]90 IR Decoder Enable 0=Normal, 1=Invert
#define VP_MASK_IR_POL 0x02 // [1]90 IR Polarity 0=Normal, 1=Invert
#define VP_MASK_IR_BASE 0x1C // [1]90 IR Clock Base
#define VP_MASK_IR_CHECK 0xE0 // [1]90 IR Check Items
#define VP_0FC_IR_ATTR2 0x0FC // IR Attribute 2
#define VP_MASK_IR_DISREPT 0x01 // [1]90 Repeat code detection enable
#define VP_MASK_IR_DB 0x06 // [1]91 IR debounce setup
#define VP_MASK_IR_TYPE 0x10 // [1]91 IR Code Type
#define VP_101_AFE_ATTR 0x101
#define VP_MASK_GPO_STATUS 0x04 // [1]20 GPO Output source select
#define VP_MASK_VD_PATH 0x10 // [1]45 Data path select
#define VP_MASK_VD_SYNC 0x20 // [1]50 Video Decoder Sync select
#define VP_MASK_VD_CLK1 0x40 // [1]27 Video Decoder Path Clock Source Select
#define VP_MASK_VD_CLK2 0x80 // [1]27 Video Decoder Path Clock Source Select
// [1]94 $7.45.2 Analog Input Path
#define VP_102_DVP_ATTR 0x102
#define VP_MASK_ANC_SEL 0x01 // [1]94 Chroma Path Select
#define VP_MASK_ANY_SEL 0x02 // [1]94 Luma Path Select
#define VP_MASK_ADC1_EN 0x04 // [1]94 ADC 1 Enable
#define VP_MASK_SEL1 0x08 // [1]94 Analog MUX Select for ADC1
#define VP_MASK_GAIN1_SEL 0x10 // ???
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