📄 vp.h
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#define VP_MASK_VHS_POL 0x10 // [1]50 External VS polarity
#define VP_MASK_EXT_SYNC 0x60 // [1]50 External Sync Enable
#define VP_052_INPUT_MODE_ATTR 0x052
#define VP_MASK_EVEN_SEL 0x03 // [1]50 EVEN/ODD Signal Select
#define VP_MASK_VISUAL_TYPE 0x04 // [1]50 Visual EVEN/ODD Mode
#define VP_MASK_SHIFT_EN 0x08 // [1]50 One Line Shift Enable
#define VP_MASK_SHIFT_BASE 0x10 // [1]50 One Line Shift Base
#define VP_MASK_CSYNC_SEL 0x20 // [1]52 CSYNC Select
#define VP_MASK_CSYNC_HS 0x40 // [1]52 CSYNC Decoder HSYNC output polarity
#define VP_MASK_CSYNC_VS 0x80 // [1]52 CSYNC Decoder VSYNC output polarity
// [1]54 $7.27 Display Window
#define VP_053_DISPLAY_V_START 0x053 // [1]54 Display Window Vertical Start Position
#define VP_054059_DISPLAY_V_END 0x054 // [1]54 Display Window Vertical End Position
#define VP_055059_DISPLAY_V_HEIGHT 0x055 // [1]54 Display Window Vertical Height
#define VP_056059_DISPLAY_H_START 0x056 // [1]54 Display Window Horizontal Start Position
#define VP_057059_DISPLAY_H_END 0x057 // [1]54 Display Window Horizontal End Position
#define VP_058059_DISPLAY_H_WIDTH 0x058 // [1]54 Display Window Horizontal Width
#define VP_059_DISPLAY_ATTR 0x059 // [1]54 Display Window Attribute
#define VP_MASK_DISPLAY_H_WIDTH_MSB 0x01
#define VP_MASK_DISPLAY_V_HEIGHT_MSB 0x02
#define VP_MASK_DISPLAY_V_END_MSB 0x04
#define VP_MASK_DISPLAY_H_START_MSB 0x30
#define VP_MASK_DISPLAY_H_END_MSB 0xC0
// [1]56 $7.28.1 Horizontal Scale Down (HSD)
#define VP_05A05C_HSD_START_P1 0x05A // [1]56 HSD Start Phase 1
#define VP_05B05C_HSD_START_P2 0x05B // [1]56 HSD Start Phase 2
#define VP_05C_HSD_START_MSB 0x05C // [1]56 HSD
#define VP_MASK_HSD_START_P1_MSB 0x0F
#define VP_MASK_HSD_START_P2_MSB 0xF0
#define VP_05D05F_HSD1_SHIFT 0x05D // [1]56 HSD Zone 1 Shift
#define VP_05E05F_HSD1_FIX 0x05E // [1]56 HSD Zone 1 Fix
#define VP_05F_HSD1_MSB 0x05F // [1]56 HSD
#define VP_MASK_HSD1_SHIFT_MSB 0x07
#define VP_MASK_HSD1_FIX_MSB 0x30
#define VP_060_HSD_ATTR 0x060 // [1]56 HSD Attribute
#define VP_MASK_HSD_EN 0x01 // [1]56 HSD Enable
#define VP_MASK_HSD_FILTER_EN 0x06 // [1]56 Filter Type
#define VP_MASK_SHAKE_MODE 0x08 // [1]56 Shake Mode
#define VP_MASK_WIDESCREEN_EN 0x40 // [1]56 Wide Screen Mode Enable
#define VP_MASK_WIDESCREEN_TYPE 0x80 // [1]56 Wide Screen Type
#define VP_061067_HSD2_SHIFT 0x061 // [1]56 HSD Zone 2 Shift
#define VP_062067_HSD2_FIX 0x062 // [1]56 HSD Zone 2 Fix
#define VP_063067_HSD3_SHIFT 0x063 // [1]56 HSD Zone 3 Shift
#define VP_064067_HSD3_FIX 0x064 // [1]56 HSD Zone 3 Fix
#define VP_065067_ANZOOM_R1 0x065 // [1]56 Nonlinear Increase Value
#define VP_066067_ANZOOM_R2 0x066 // [1]56 Nonlinear Decrease Value
#define VP_067_ANZOOM_ATTR 0x067 // [1]56 HSD Attribute
// [1]57 $7.28.2 Vertical Scale Down (VSD)
#define VP_06806A_VSD_START_EVEN_M0 0x068 // [1]57 VSD EVEN Field Start
#define VP_06906A_VSD_START_ODD_M0 0x069 // [1]57 VSD ODD Field Start
#define VP_06B06D_VSD_SHIFT_M0 0x06B // [1]57 VSD Shift
#define VP_06C06D_VSD_FIX_M0 0x06C // [1]57 VSD Fix
#define VP_06D_VSD_ATTR_M0 0x06D // [1]57 VSD Attribute
#define VP_MASK_VSD_EN_M0 0x01 // [1]57 VSD Enable
#define VP_MASK_VSD_FILTER_EN_M0 0x06 // [1]57 VSD Filter Enable
#define VP_MASK_CUT_AUTO_M0 0x08 // [1]57
#define VP_MASK_VSD_SHIFT_MSB_M0 0x10 // [1]57
#define VP_MASK_LINE_CUT_M0 0x20 // [1]57
#define VP_MASK_VSD_FIX_MSB_M0 0x40 // [1]57
#define VP_MASK_CUT_MODE_M0 0x80 // [1]57
// [1]59 $7.29 Timing Adjustment
#define VP_06E070_DELAY_IHS_EVEN_M0 0x06E // [1]59 Even Field outputs VS delay in IHS
#define VP_06F070_DELAY_IHS_ODD_M0 0x06F // [1]59 Odd Field outputs VS delay in IHS
#define VP_070_DELAY_IHS_M0 0x070 // [1]59 VS delay
#define VP_MASK_DELAY_IHS_ODD_M0_MSB 0x03
#define VP_MASK_DELAY_IHS_EVEN_M0_MSB 0x30
// [1]57 $7.28.2 Vertical Scale Down (VSD)
#define VP_071073_VSD_START_EVEN_M1 0x071 // [1]57 VSD EVEN Field Start
#define VP_072073_VSD_START_ODD_M1 0x072 // [1]58 VSD ODD Field Start
#define VP_074076_VSD_SHIFT_M1 0x074 // [1]58 VSD Shift
#define VP_075076_VSD_FIX_M1 0x075 // [1]58 VSD Fix
#define VP_076_VSD_ATTR_M1 0x076 // [1]58 VSD Attribute
#define VP_MASK_VSD_EN_M1 0x01 // [1]58 VSD Enable
#define VP_MASK_VSD_FILTER_EN_M1 0x06 // [1]58 VSD Filter Enable
#define VP_MASK_CUT_AUTO_M1 0x08
#define VP_MASK_VSD_SHIFT_MSB_M1 0x10
#define VP_MASK_LINE_CUT_M1 0x20
#define VP_MASK_VSD_FIX_MSB_M1 0x40
#define VP_MASK_CUT_MODE_M1 0x80
// [1]59 $7.29 Timing Adjustment
#define VP_077079_DELAY_IHS_EVEN_M1 0x077 // [1]59 Even Field outputs VS delay in IHS
#define VP_078079_DELAY_IHS_ODD_M1 0x078 // [1]59 Odd Field outputs VS delay in IHS
#define VP_079_DELAY_IHS_M1 0x079 // [1]59 VS delay
#define VP_MASK_DELAY_IHS_ODD_M1_MSB 0x03
#define VP_MASK_DELAY_IHS_EVEN_M1_MSB 0x30
#define VP_07B_RGBOUT_DLYO 0x07B // RGB odd field out delay
// [1]63 $7.30 Brightness/Contrast Adjustment
#define VP_07C_BRIGHTNESS_R 0x07C // [1]63 R Brightness
#define VP_07D_BRIGHTNESS_G 0x07D // [1]63 G Brightness
#define VP_07E_BRIGHTNESS_B 0x07E // [1]63 B Brightness
#define VP_07F_CONTRAST_R 0x07F // [1]63 R Contrast
#define VP_080_CONTRAST_G 0x080 // [1]63 G Contrast
#define VP_081_CONTRAST_B 0x081 // [1]63 B Contrast
// [1]65 $7.31 Image Enhancement
#define VP_082_BLACK_LEVEL 0x082 // [1]65
#define VP_083_WHITE_SLOPE 0x083
#define VP_084_BLACK_SLOPE 0x084
#define VP_085_WHITE_START 0x085
#define VP_086_BLACK_START 0x086
// [1]68 $7.31.3 UV Domain Process
#define VP_087_U_GAIN 0x087 // [1]68
#define VP_088_V_GAIN 0x088
// [1]69 $7.31.4 Chroma Transient Improvement (CTI)
#define VP_089_CTI_ATTR 0x089
#define VP_MASK_CTI_EN 0x01 // [1]69 CTI Enable
#define VP_MASK_CTI_BW 0x06 // [1]69 CTI Bandwidth Select
#define VP_MASK_CTI_COMP 0x18 // [1]69 CTI Compare Select
#define VP_MASK_CTI_GAIN 0xE0 // [1]69 CTI Gain Value
// [1]75 $7.34 Color Space Conversion
#define VP_08A_CTI_CORING 0x08A
#define VP_MASK_CTI_CORING 0x0F // [1]69 CTI Coring Value
#define VP_MASK_Y2R_SEL 0x10 // [1]75 Color Space Conversion
#define VP_MASK_BRIGHTNESS_SEL 0x20 // [1]63 Brightness Type Select
#define VP_MASK_ZERO1_EN 0x40 // [1]41 Blank enable before image process
#define VP_MASK_ZERO2_EN 0x80 // [1]41 Blank enable after image process
// [1]67 $7.31.2 Image Enhancement
#define VP_08B_IMAGE_ATTR 0x08B // Image Enhancement
#define VP_MASK_HUE_EN 0x01 // [1]68 HUE Enable
#define VP_MASK_CONTRAST_TYPE 0x02 // [1]63 Contrast Type
#define VP_MASK_COLOR_KILL 0x04 // [1]68 Color kill Enable
#define VP_MASK_DITHER_EN 0x08 // [1]74 Dither Enable
#define VP_MASK_FILTER_TYPE 0x70 // [1]67 YUV Domain Image Filter Type
#define VP_MASK_FILTER_EN 0x80 // [1]67 YUV Domain Image Enhance Enable
// [1]74 $7.33 Dither
#define VP_08C_DITHER_EVEN 0x08C // [1]74 EVEN Field Dither Factor
#define VP_08D_DITHER_ODD 0x08D // [1]74 Odd Field Dither Factor
// [1]68 $7.31.3 UV Domain Process
#define VP_08E_HUE_COS 0x08E // [1]68 Hue COS
#define VP_08F_HUE_SIN 0x08F // [1]68 Hue SIN
#define VP_090_U_MAX 0x090 // [1]68 U Maximum Threshold
#define VP_091_U_MIN 0x091 // [1]68 U Minimum Threshold
#define VP_092_V_MAX 0x092 // [1]68 V Maximum Threshold
#define VP_093_V_MIN 0x093 // [1]68 V Minimum Threshold
// [1]71 $7.32.1 Adjust-Curve
#define VP_094_RANGE1 0x094 // [1]72 Range 1 End Position
#define VP_095_RANGE2 0x095 // [1]72 Range 2 End Position
#define VP_096_RANGE3 0x096 // [1]72 Range 3 End Position
#define VP_097_RANGE4 0x097 // [1]72 Range 4 End Position
#define VP_098_RANGE5 0x098 // [1]72 Range 5 End Position
#define VP_099_RANGE6 0x099 // [1]72 Range 6 End Position
#define VP_094_099_RANGE 0x094 // [1]72 Range
#define VP_09A_SLOPE1 0x09A // [1]72 Range 1 Slope
#define VP_09B_SLOPE2 0x09B // [1]72 Range 2 Slope
#define VP_09C_SLOPE3 0x09C // [1]72 Range 3 Slope
#define VP_09D_SLOPE4 0x09D // [1]72 Range 4 Slope
#define VP_09E_SLOPE5 0x09E // [1]72 Range 5 Slope
#define VP_09F_SLOPE6 0x09F // [1]72 Range 6 Slope
#define VP_0A0_SLOPE7 0x0A0 // [1]72 Range 7 Slope
#define VP_09A_0A0_SLOPE 0x09A // [1]72 Range Slope
#define VP_0A1_DI_OFFSET 0x0A1 // [1]72 RGB output data offset
// [1]73 $7.32.2 LUT Correction
#define VP_0A2_GAMMA_ATTR 0x0A2
#define VP_MASK_GAMMA_LUT_EN 0x01 // [1]73 Gamma LUT Enable
#define VP_MASK_GAMMA_CURVE_EN 0x02 // [1]72 Gamma Curve Enable
#define VP_MASK_GAMMA_LUT_MODE 0x04 // [1]73 Gamma LUT RAM Mapping Mode
// [1]76 $7.35 PLL and OSC Pads
#define VP_0A4_PLL_VND 0x0A4 // [1]76 PLL N Value
#define VP_0A50A6_PLL_VMD 0x0A5 // [1]76 PLL M Value
#define VP_0A6_PLL_ATTR1 0x0A6 // [1]76
#define VP_MASK_PLL_VMD_MSB 0x07 // [1]76
#define VP_MASK_PLL_VMTDIV 0x08 // [1]76 Output clock test enable
#define VP_MASK_PLL_VPD 0x70 // [1]76 PLL D Value
#define VP_MASK_PLL_HALFCK 0x80 // [1]76 Half clock output
#define VP_0A7_PLL_ATTR2 0x0A7 // [1]76
#define VP_MASK_PLL_LEN 0x01 // [1]76 Lock enable
#define VP_MASK_PLL_VPRST 0x02 // [1]76 VCO Reset
#define VP_MASK_PLL_VPLPFS 0x04 // [1]76 PLL Lpf select
#define VP_MASK_PLL_VFSEL 0x08 // [1]76 VCO frequency range select
#define VP_MASK_PLL_R 0x30 // [1]76 REF skew control
#define VP_MASK_PLL_S 0xC0 // [1]76 SEL skew control
// [1]77 $7.36 TIMER
#define VP_0BA_TIMER0_COUNT 0x0BA // [1]77 Timer0 Count value
#define VP_0BB_TIMER0_ATTR 0x0BB // [1]77 Timer0 Attribute
#define VP_MASK_TIMER0_BASE_MODE 0x03 // [1]77 Timer0 Count Base
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