📄 vp.h
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#define VP_023024_V_TOTAL_LENGTH 0x023 // [1]28 PANEL Vertical Total Length
// [1]29 $7.10 Output Data Path
#define VP_024_OUTPUT_DATAPATH 0x024 // [1]29 OUTPUT data path
#define VP_MASK_V_TOTAL_LENGTH 0x01 // [1]28 PANEL Vertical Total Length MSB
#define VP_MASK_V_ACTIVE_END 0x02 // [1]28 PANEL Active Window Vertical End Position MSB
#define VP_MASK_SWAPE_ORB 0x04 // [1]29 R EVEN Data bus swap B Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPE_ORG 0x08 // [1]29 R EVEN Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPE_OGB 0x10 // [1]29 R EVEN Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_ORB 0x20 // [1]29 R ODD Data bus swap B Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_ORG 0x40 // [1]29 R ODD Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_OGB 0x80 // [1]29 R ODD Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_ACTIVE_TOTAL (VP_MASK_V_ACTIVE_END | VP_MASK_V_TOTAL_LENGTH)
// [1]29 $7.10 Output Data Path
#define VP_025_OUTPUT_ATTR 0x025 // [1]29 OUTPUT data path
#define VP_MASK_ROUT_POL 0x01 // [1]29 R Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_GOUT_POL 0x02 // [1]29 G Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_BOUT_POL 0x04 // [1]29 B Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_SERIAL_OUT 0x08 // [1]31 Output Clock Polarity 0=Normal, 1=Invert
#define VP_MASK_ROUT_ROT 0x10 // [1]29 R Data Rotate 0=Disable, 1=Invert
#define VP_MASK_GOUT_ROT 0x20 // [1]29 G Data Rotate 0=Disable, 1=Invert
#define VP_MASK_BOUT_ROT 0x40 // [1]29 B Data Rotate 0=Disable, 1=Invert
#define VP_MASK_OCLK_POL 0x80 // [1]29 Output Clock Polarity
// [1]32 $7.12 Special Output Setup
#define VP_026_SPECIAL_OUTPUT 0x026 // [1]32
#define VP_MASK_RTS1 0x07 // [1]32 RTS1 Selection
#define VP_MASK_RTS2 0x70 // [1]32 RTS2 Selection
#define VP_MASK_SWAP_SRC 0x08 // ???
#define VP_MASK_PROTECT_MODE 0x80 // [1]33 Miinimum Output Lines protect
// [1]34 $7.14 TCON Function
#define VP_027029_STV_START 0x027 // [1]34 STV Signal Start[7:0]
#define VP_028029_STV_END 0x028 // [1]34 STV Signal End[7:0]
#define VP_029_STV_ATTR 0x029 // [1]34 STV Attribute
#define VP_MASK_STV_START_MSB 0x01 // [1]34 STV Signal Start[8]
#define VP_MASK_STV_END_MSB 0x02 // [1]34 STV Signal End[8]
#define VP_MASK_VCOM_TYPE 0x0C // [1]34 VCOM Signal TYPE
#define VP_MASK_FRP_POL 0x10 // [1]34 FRP Output Polarity
#define VP_MASK_CPH_HALF 0x20 // [1]36 TCON Clock Output Mode
#define VP_MASK_3CLK_SEL 0x40 // [1]36 Clock Type Select
#define VP_MASK_CPH_MODE 0x80 // [1]36 CPH Clcok Mode
#define VP_02A02E_STH_START 0x02A // [1]34 STH Signal Start[7:0]
#define VP_02B02E_STH_END 0x02B // [1]34 STH Signal End[7:0]
#define VP_02C02E_CKV_START 0x02C // [1]34 CKV Signal Start[7:0]
#define VP_02D02E_CKV_END 0x02D // [1]34 CKV Signal End[7:0]
#define VP_02F033_LD_START 0x02F // [1]34 LD Signal Start[7:0]
#define VP_030033_LD_END 0x030 // [1]34 LD Signal End[7:0]
#define VP_031033_OEH_START 0x031 // [1]34 OEH Signal Start[7:0]
#define VP_032033_OEH_END 0x032 // [1]34 OEH Signal End[7:0]
#define VP_033_LD_OEH_ATTR 0x033 // [1]34 LD/OEH Attribute
#define VP_MASK_OEH_START_MSB 0x03 // [1]34 OEH Signal Start
#define VP_MASK_OEH_END_MSB 0x0C // [1]34 OEH Signal End
#define VP_MASK_LD_START_MSB 0x30 // [1]34 LD Signal Start
#define VP_MASK_LD_END_MSB 0xC0 // [1]34 LD Signal End
#define VP_034035_VCOM_SHIFT 0x034 // [1]34 VCOM Shift
#define VP_035_TCON_ATTR1 0x035 // [1]34 TCON Attribute 1
#define VP_MASK_VCOM_SHIFT_MSB 0x03 // [1]34 VCOM Shift[9:8]
#define VP_MASK_BUS_INV 0x0C // [1]34 Data Bus Control
#define VP_MASK_CPH3_PHASE 0x70 // [1]37 CPH3 clock delay phase
#define VP_MASK_CPH3_POL 0x80 // [1]37 CPH3 clock polarity
#define VP_036_TCON_GPO 0x036 // [1]34 TCON GPO
#define VP_MASK_OEH_POL 0x01 // [1]34 OEH Output Polarity
#define VP_MASK_STH_POL 0x02 // [1]34 STH Output Polarity
#define VP_MASK_STV_POL 0x04 // [1]34 STV Output Polarity
#define VP_MASK_TCON_GPO 0x38 // [1]34 TCON GPO
#define VP_MASK_OEH_GATE 0x40 // [1]35 OEH gated with ODE
#define VP_MASK_LTPS_MODE 0x80 // [1]35 LTPS Mode select
#define VP_037_TCON_ATTR2 0x037 // [1]35 TCON Attribute 2
#define VP_MASK_STH_SEL 0x01 // [1]35 STH Output Selection
#define VP_MASK_STV_SEL 0x02 // [1]35 STV Output Selection
#define VP_MASK_TCON_RL 0x04 // [1]35 TCON R/L
#define VP_MASK_TCON_UD 0x08 // [1]35 TCON U/D
#define VP_MASK_Q2H_POL 0x10 // [1]35 Q2H Output Polarity
#define VP_MASK_LD_POL 0x20 // [1]35 LD Output Polarity
#define VP_MASK_CKV_POL 0x40 // [1]35 CKV Output Polarity
#define VP_MASK_TCON_EN 0x80 // [1]35 TCON Enable
#define VP_MASK_TCON_UD_RL (VP_MASK_TCON_RL | VP_MASK_TCON_UD)
#define VP_MASK_TCON_Q2H_UD_RL (VP_MASK_Q2H_POL | VP_MASK_TCON_RL | VP_MASK_TCON_UD)
#define VP_MASK_TCON_Q2H_UD_RL_STV_STH (VP_MASK_Q2H_POL | VP_MASK_TCON_RL | VP_MASK_TCON_UD | VP_MASK_STV_SEL | VP_MASK_STH_SEL)
#define VP_038_TCON_ATTR3 0x038 // [1]36 TCON Attribute 3
#define VP_MASK_CPH1_PHASE 0x07 // [1]36 CPH1 clock delay phase
#define VP_MASK_CPH1_POL 0x08 // [1]36 CPH1 clock polarity
#define VP_MASK_CPH2_PHASE 0x70 // [1]36 CPH2 clock delay phase
#define VP_MASK_CPH2_POL 0x80 // [1]37 CPH2 clock polarity
#define VP_039_TCON_ATTR4 0x039 // [1]37 TCON Attribute 4
#define VP_MASK_CPH1_SEL_M0 0x03 // [1]37 CPH1 Source Select for Even Field
#define VP_MASK_CPH2_SEL_M0 0x0C // [1]37 CPH2 Source Select for Even Field
#define VP_MASK_CPH3_SEL_M0 0x30 // [1]37 CPH3 Source Select for Even Field
#define VP_MASK_CPH1_EN 0x40 // [1]37 CPH1 output enable
#define VP_MASK_TCON_SYNC 0x80 // [1]38 STH,STV,UD and Q2H synchronize with VS
#define VP_03A_TCON_ATTR5 0x03A // [1]37 TCON Attribute 5
#define VP_MASK_CPH1_SEL_M1 0x03 // [1]37 CPH1 Source Select for Odd Field
#define VP_MASK_CPH2_SEL_M1 0x0C // [1]37 CPH2 Source Select for Odd Field
#define VP_MASK_CPH3_SEL_M1 0x30 // [1]37 CPH3 Source Select for Odd Field
#define VP_MASK_CPH2_EN 0x40 // [1]37 CPH2 output enable
#define VP_MASK_CPH3_EN 0x80 // [1]37 CPH3 output enable
// [1]41 $7.18 Background 2
#define VP_03B_TESTPAT2_ATTR 0x03B // [1]41
#define VP_MASK_BG2_G 0x03 // [1]41 Background 2
#define VP_MASK_BG2_B 0x0C // [1]41 Background 2
#define VP_MASK_BG2_R 0x30 // [1]41 Background 2
// [1]42 $7.19 Background and Test Pattern
#define VP_03C_TESTPAT_R 0x03C // [1]42 Test Pattern RED Color
#define VP_03D_TESTPAT_G 0x03D // [1]42 Test Pattern GREEN Color
#define VP_03E_TESTPAT_B 0x03E // [1]42 Test Pattern BLUE Color
#define VP_03F_TESTPAT_RATIO 0x03F // [1]42 Test Pattern Ratio
#define VP_040_TESTPAT_ATTR 0x040 // [1]42 Test Pattern Attribute
#define VP_MASK_PATTERN_TYPE 0x07 // Test Pattern Type
#define VP_MASK_PATTERN_HV 0x10 // Test Pattern HV
#define VP_MASK_PATTERN_DIR 0x20 // Test Pattern Direction
#define VP_MASK_BACKGROUND_EN 0x40 // Background Mode Enable 0=Disable, 1=Enable
#define VP_MASK_FREERUN_EN 0x80 // Free-Run Mode Enable
#define VP_MASK_PATTERN_TYPE_4096 0x00 // [1]23 Pure 4096 Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_R 0x01 // [1]23 Ramp R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_G 0x02 // [1]23 Ramp G Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_GR 0x03 // [1]23 Ramp G+R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_B 0x04 // [1]23 Ramp B Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BR 0x05 // [1]23 Ramp B +R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BG 0x06 // [1]23 Ramp B+G Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BGR 0x07 // [1]23 Ramp B+G+R Color Pattern
#define VP_FREERUN_ON VP_MASK_FREERUN_EN
#define VP_FREERUN_OFF 0x00
// [1]43 $7.20 Auto Blue Screen
#define VP_041_AUTOON 0x041 // [1]43 Auto ON
#define VP_MASK_AUTOON_TIME 0x7F
#define VP_MASK_AUTOON_EN 0x80
// [1]44 $7.21 Input Image Windows Setup
#define VP_042044_INPUT_H_START_M0 0x042 // [1]44 Input Window Horizontal Start Position Mode 0
#define VP_043044_INPUT_H_END_M0 0x043 // [1]44 Input Window Horizontal End Position Mode 0
#define VP_044_INPUT_H_M0 0x044 // [1]44 Input Window Horizontal Mode 0
#define VP_MASK_INPUT_H_START_M0_MSB 0x07
#define VP_MASK_INPUT_H_END_M0_MSB 0x70
#define VP_045047_INPUT_V_START_M0 0x045 // [1]44 Input Window Vertical Start Position Mode 0
#define VP_046047_INPUT_V_END_M0 0x046 // [1]44 Input Window Vertical End Position Mode 0
#define VP_047_INPUT_V_M0 0x047 // [1]44 Input Window Vertical Mode 0
#define VP_MASK_INPUT_V_START_M0_MSB 0x07
#define VP_MASK_INPUT_V_END_M0_MSB 0x70
#define VP_04804A_INPUT_H_START_M1 0x048 // [1]44 Input Window Horizontal Start Position Mode 1
#define VP_04904A_INPUT_H_END_M1 0x049 // [1]44 Input Window Horizontal End Position Mode 1
#define VP_04A_INPUT_H_M1 0x04A // [1]44 Input Window Horizontal
#define VP_MASK_INPUT_H_START_M1_MSB 0x07
#define VP_MASK_INPUT_H_END_M1_MSB 0x70
#define VP_04B04D_INPUT_V_START_M1 0x04B // [1]44 Input Window Vertical Start Position Mode 1
#define VP_04C04D_INPUT_V_END_M1 0x04C // [1]44 Input Window Vertical End Position Mode 1
#define VP_04D_INPUT_V_M1 0x04D // [1]44 Input Window Vertical Mode 1
#define VP_MASK_INPUT_V_START_M1_MSB 0x07
#define VP_MASK_INPUT_V_END_M1_MSB 0x70
// [1]45 $7.22 Input Data Path
#define VP_04E_INPUT_DATAPATH 0x04E // [1]45 Input Data Path
#define VP_MASK_RIN_POL 0x01 // [1]45 R Data Input Polarity
#define VP_MASK_GIN_POL 0x02 // [1]45 G Data Input Polarity
#define VP_MASK_BIN_POL 0x04 // [1]45 B Data Input Polarity
#define VP_MASK_RIN_ROT 0x08 // [1]45 R Data Rotate
#define VP_MASK_GIN_ROT 0x10 // [1]45 G Data Rotate
#define VP_MASK_BIN_ROT 0x20 // [1]45 B Data Rotate
#define VP_MASK_AUTO_SWITCH 0x40 // [1]53 Auto Switch Mode
#define VP_MASK_SWITCH_MODE 0x80 // [1]53 Switch Mode (0=Mode0, 1=Mode1)
#define VP_04F_INPUT_ATTR 0x04F // [1]45 Input Data Path Attribute
#define VP_MASK_ISWAP_RB 0x01 // [1]45 Swap R/B Data Bus
#define VP_MASK_ISWAP_RG 0x02 // [1]45 Swap R/B Data Bus
#define VP_MASK_ISWAP_GB 0x04 // [1]45 Swap G/B Data Bus
#define VP_MASK_RIN_EN 0x10 // [1]45 R Data Input Port Enable
#define VP_MASK_GIN_EN 0x20 // [1]45 G Data Input Port Enable
#define VP_MASK_BIN_EN 0x40 // [1]45 B Data Input Port Enable
// [1]49 $7.24 Input Mode Selection
#define VP_050_INPUT_MODE 0x050
#define VP_MASK_IMODE 0x01 // [1]49 Input Mode Select
#define VP_MASK_SRC_SEL 0x06 // [1]49 Source Select
#define VP_MASK_PIXEL_MODE 0x18 // [1]49 Input Active Pixel Mode
#define VP_MASK_MCLK_MODE 0xE0 // [1]27 MCLK Domain Clock source select
#define VP_051_INPUT_MODE_POLARITY 0x051
#define VP_MASK_SORT_656 0x07 // [1]49 Data sequence Control
#define VP_MASK_IHS_POL 0x08 // [1]50 External HS polarity
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