vp.h

Bitek 公司 bit1611b模拟屏驱动芯片外接MCU驱动DEMO源码

/* **********************************************************************

         Copyright (c) 2002-2006 Beyond Innovation Technology Co., Ltd

        All rights are reserved. Reproduction in whole or in parts is
    prohibited without the prior written consent of the copyright owner.
   ----------------------------------------------------------------------

    Module: VP.H - Video Processor.

    Purpose: Interface of VP module.

    Version: 0.01                                   08:33PM  2005/12/27

    Compiler: Keil 8051 C Compiler v8.01

    Reference:
    [1] BIT1611B Data Sheet Version 1.0, 2005-11-10,
        Beyond Innovation Technology

   ----------------------------------------------------------------------
    Modification:

    R0.01 08:33PM  2005/12/27 Jeffrey Chang
    Reason:
        1. Original.
    Solution:

   ********************************************************************** */

#ifndef _VP_H_
#define _VP_H_


/* ------------------------------------
    Header Files
   ------------------------------------ */
#include "eeprom.h"
#include "platform.h"

/* ------------------------------------
    Macro Definitions
   ------------------------------------ */
#undef EXTERN

#ifdef _VP_C_
    #define EXTERN
#else
    #define EXTERN extern
#endif


/* ::::::::::::::::::::::::::::::::::::
    VP Register Definitions
   :::::::::::::::::::::::::::::::::::: */

// [1]11 $7.1 Hardware Version
#define VP_000_HW_VER                       0x000       // [1]11 Hardware version
    #define VP_MASK_HW_VER                      0xC6    // 7 6 5 4 3 2 1 0
                                                        // | | | | | | |_|_ Product Version
                                                        // | | | |_|_|_____ Product Number
                                                        // |_|_|___________ Product Group
                                                        // 1 1 0 0 0 1 1 0  0xC6

#define VP_001_SW_VER                       0x001       // [1]11 Softwre version

// [1]12 $7.2 Interrupt (FLAG, MASK and ACK)
#define VP_002_INT_FLAG                     0x002       // [1]12 Interrupt Flag
    #define VP_MASK_HASSIG_FLAG                 0x01    // [1]12 Signal Ready by HSYNC  Revised by JC 01:15PM  2006/02/10
    #define VP_MASK_NOSIG_FLAG                  0x02    // [1]12 No Signal by HSYNC
    #define VP_MASK_MODE_FLAG                   0x04    // [1]12 VSYNC changes
    #define VP_MASK_VSYNC_FLAG                  0x08    // [1]12 VSYNC falling edge
    #define VP_MASK_ERROR1_FLAG                 0x10    // [1]12 Timer 1 or Line Buffer Error 1 error
    #define VP_MASK_ERROR2_FLAG                 0x20    // [1]12 Timer 2 or Line Buffer Error 2 error
    #define VP_MASK_IR_FLAG                     0x40    // [1]12 IR Remote Control Detection
    #define VP_MASK_KEY_FLAG                    0x80    // [1]12 GPI Detection

#define VP_003_INT_MASK                     0x003       // [1]12 Interrupt Mask
    #define VP_MASK_HASSIG_MASK                 0x01    // Signal Ready by HSYNC    Revised by JC 01:15PM  2006/02/10
    #define VP_MASK_NOSIG_MASK                  0x02    // No Signal by HSYNC
    #define VP_MASK_MODE_MASK                   0x04    // VSYNC changes
    #define VP_MASK_VSYNC_MASK                  0x08    // VSYNC falling edge
    #define VP_MASK_UNDER_MASK                  0x10    // Timer 1 or Line Buffer Error 1 error
    #define VP_MASK_OVER_MASK                   0x20    // Timer 2 or Line Buffer Error 2 error
    #define VP_MASK_IR_MASK                     0x40    // IR Remote Control Detection
    #define VP_MASK_KEY_MASK                    0x80    // GPI Detection

#define VP_004_INT_ACK                      0x004       // [1]13 Interrupt ACK
    #define VP_MASK_HASSIG_ACK                  0x01    // Signal Ready by HSYNC    Revised by JC 01:15PM  2006/02/10
    #define VP_MASK_NOSIG_ACK                   0x02    // No Signal by HSYNC
    #define VP_MASK_MODE_ACK                    0x04    // VSYNC changes
    #define VP_MASK_VSYNC_ACK                   0x08    // VSYNC falling edge
    #define VP_MASK_UNDER_ACK                   0x10    // Timer 1 or Line Buffer Error 1 error
    #define VP_MASK_OVER_ACK                    0x20    // Timer 2 or Line Buffer Error 2 error
    #define VP_MASK_IR_ACK                      0x40    // IR Remote Control Detection
    #define VP_MASK_KEY_ACK                     0x80    // GPI Detection

#define VP_005_INT_ATTR                     0x005       // [1]13 Interrupt Attribute
    #define VP_MASK_INT_TYPE                    0x01    // [1]13 0=Edge, 1=Level
    #define VP_MASK_INT_POL                     0x02    // [1]13 1=Low/Falling Active, 0=High/Rising Active
    #define VP_MASK_ERROR_TYPE                  0x04    // [1]13 0=ODD Field, 1=EVEN Field
    #define VP_MASK_LOAD_IN                     0x10    // [1]15 Double Buffer Load Enable
    #define VP_MASK_LOAD_TYPE                   0x20    // [1]15 Double Buffer Register Update Type
    #define VP_MASK_INT_VSSEL                   0x40    // [1]13 Interrupt Vecotr[3] source select
    #define VP_MASK_INT_ERREL                   0x80    // [1]13 Interrupt Vecotr[5:4] source select

// [1]19 $7.4 Pad Type Setup
#define VP_007_PORT_ATTR                    0x007       // [1]19 Port Attribute
    #define VP_MASK_ROUT_TRI                    0x01    // [1]19 ROUT Port Tri-state enable
    #define VP_MASK_GOUT_TRI                    0x02    // [1]19 GOUT Port Tri-state enable
    #define VP_MASK_BOUT_TRI                    0x04    // [1]19 BOUT Port Tri-state enable
    #define VP_MASK_OCLK_TRI                    0x08    // [1]19 OCLK Pin  Tri-state enable
    #define VP_MASK_ODE_TRI                     0x10    // [1]19 ODE  Pin  Tri-state enable
    #define VP_MASK_INT_TRI                     0x20    // [1]19 INT  Pin  Tri-state enable

// [1]20 $7.5 GPO Function
#define VP_008_GPO_SEL                      0x008       // [1]20 GPO Enable 0=Disable, 1=Enable
#define VP_009_GPO_TYPE                     0x009       // [1]20 GPO Type 0=Normal, 1=Tri-State
    #define VP_MASK_GPO_TYPE                    0x3F    // [1]20 GPO Type
    #define VP_MASK_REGS_CLKEN                  0x80    // ???

#define VP_00A_GPO_REG                      0x00A       // [1]20 GPO Value 0=Low Level, 1=High Level


// [1]23 $7.6.2 Software Reset
#define VP_00B_SRST_ATTR1                   0x00B       // [1]23 Software Reset
    #define VP_MASK_SYNCDET_EN                  0x01    // [1]23 SYNCDET        Software Reset
    #define VP_MASK_PWM1_EN                     0x02    // [1]23 PWM1           Software Reset
    #define VP_MASK_PWM2_EN                     0x04    // [1]23 PWM2           Software Reset
    #define VP_MASK_PWM3_EN                     0x08    // [1]23 PWM3           Software Reset
    #define VP_MASK_PWM4_EN                     0x10    // [1]23 PWM4           Software Reset
    #define VP_MASK_SAMPLE_EN                   0x20    // [1]23 SAMPLE         Software Reset
    #define VP_MASK_OSD_CLKEN                   0x40    // ???
    #define VP_MASK_PLL_SRC                     0x80    // [1]76 PLL base clock select

#define VP_00C_SRST_ATTR2                   0x00C       // [1]23 Software Reset
    #define VP_MASK_SRST_VP                     0x01    // [1]23 PWM            Software Reset
    #define VP_MASK_SRST_OUT                    0x02    // [1]23 Power          Software Reset
    #define VP_MASK_SRST_OSD                    0x04    // [1]23 OSD            Software Reset
    #define VP_MASK_SRST_CHROMA                 0x08    // [1]23 Chroma         Software Reset
    #define VP_MASK_SRST_SYNC                   0x10    // [1]23 SYNC           Software Reset
    #define VP_MASK_SRST_CLOCK                  0x20    // [1]23 Clock          Software Reset
    #define VP_MASK_SRST_AGC                    0x40    // [1]23 AGC            Software Reset
    #define VP_MASK_SRST_COMB                   0x80    // [1]23 Comb Filter    Software Reset


// [1]25 $7.7 Built-in DAC
#define VP_00E_CLK_ATTR1                    0x00E       // [1]25
    #define VP_MASK_XCLK_SEL                    0x03    // [1]26 XCLK Clock Domain Source Select
    #define VP_MASK_DACCLK_MODE                 0x0C    // [1]25 DAC Clock Phase Select
    #define VP_MASK_DAC_POL                     0x10    // [1]25 DAC LCLK Source polarity
    #define VP_MASK_DAC_SEL                     0x20    // [1]25 DAC Clock polarity
    #define VP_MASK_DAC_DG                      0x40    // [1]25 DAC Noise Reduce
    #define VP_MASK_DAC_EN                      0x80    // [1]25 DAC Enable

// [1]26 $7.8 Clock Domain Systems
#define VP_00F_CLK_ATTR2                    0x00F       // [1]26
    #define VP_MASK_LCLK_EN                     0x01    // [1]26 LCLK Enable: 0=Disable, 1=Enable
    #define VP_MASK_LCLK_POL                    0x02    // [1]26 LCLK Domain Polarity
    #define VP_MASK_LCLK_SEL                    0x0C    // [1]26 CLK Domain Clock Source Select
    #define VP_MASK_PCLK_EN                     0x10    // [1]26 PCLK Domain Enable: 0=Disable, 1=Enable
    #define VP_MASK_PCLK_POL                    0x20    // [1]26 PCLK Domain Polarity: 0=Normal, 1=Invert
    #define VP_MASK_PCLK_SEL                    0x40    // [1]26 PCLK Domain Clock Source Select
    #define VP_MASK_DELTA_MODE                  0x80    // ???

// [1]28 $7.9 Panel Timing
#define VP_010013_HSYNC_PULSE_WIDTH         0x010       // [1]28 PANEL HSYNC Pulse Width
#define VP_011013_H_ACTIVE_START            0x011       // [1]28 PANEL Active Window Horizontal Start Position
#define VP_012013_H_ACTIVE_END              0x012       // [1]28 PANEL Active Window Horizontal End Position

#define VP_013_PANEL_H_ATTR                 0x013
    #define VP_MASK_H_ACTIVE_END_MSB            0x03    // [1]28
    #define VP_MASK_H_ACTIVE_START_MSB          0x0C    // [1]28
    #define VP_MASK_HSYNC_PULSE_WIDTH_MSB       0x30    // [1]28
    #define VP_MASK_SYNCO_EN                    0x40    // [1]33 Sync with input VSYNC
    #define VP_MASK_SYNCO_MODE                  0x80    // [1]33 Two-Field Synchronization mode select

#define VP_014016_H_TOTAL_LENGTH_EVEN_M0    0x014       // [1]28 PANEL EVEN Field Horizontal Total Length
#define VP_015016_H_TOTAL_LENGTH_ODD_M0     0x015       // [1]28 PANEL ODD Field Horizontal Total Length
#define VP_016_H_TOTAL_LENGTH_M0            0x016
    #define VP_MASK_H_TOTAL_LENGTH_ODD_M0_MSB   0x03    // [1]28
    #define VP_MASK_H_TOTAL_LENGTH_EVEN_M0_MSB  0x30    // [1]28

// [1]59 $7.29 Timing Adjustment
#define VP_017019_DELAY_OCLK_M0_EVEN        0x017       // [1]59 Even Field outputs VS delay    in OCLK
#define VP_018019_DELAY_OCLK_M0_ODD         0x018       // [1]59 Odd Field outputs VS delay     in OCLK


// [1]28 $7.9 Panel Timing
#define VP_01A01C_H_TOTAL_LENGTH_EVEN_M1    0x01A       // [1]28 PANEL EVEN Field Horizontal Total Length
#define VP_01B01C_H_TOTAL_LENGTH_ODD_M1     0x01B       // [1]28 PANEL ODD Field Horizontal Total Length
#define VP_01C_H_TOTAL_LENGTH_M1            0x01C
    #define VP_MASK_H_TOTAL_LENGTH_ODD_M1_MSB   0x03    // [1]28
    #define VP_MASK_H_TOTAL_LENGTH_EVEN_M1_MSB  0x30    // [1]28

// [1]59 $7.29 Timing Adjustment
#define VP_01D01F_DELAY_OCLK_M1_EVEN        0x01D       // [1]59 Even Field outputs VS delay    in OCLK
#define VP_01E01F_DELAY_OCLK_M1_ODD         0x01E       // [1]59 Odd Field outputs VS delay     in OCLK

// [1]28 $7.9 Panel Timing
#define VP_020_VSYNC_PULSE_WIDTH            0x020       // [1]28 PANEL VSYNC Pulse Width
#define VP_021_V_ACTIVE_START               0x021       // [1]28 PANEL Active Window Vertical Start Position

#define VP_022024_V_ACTIVE_END              0x022       // [1]28 PANEL Active Window Vertical End Position