de2_ccd.map.eqn

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

--B1L111 is VGA_Controller:u1|oVGA_R[7]~275
B1L111 = GB4_q_a[7] & B1L114 & B1L115;


--GB4_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[8]_PORT_A_data_in = VCC;
GB4_q_a[8]_PORT_A_data_in_reg = DFFE(GB4_q_a[8]_PORT_A_data_in, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_data_in = G1_mDATAOUT[8];
GB4_q_a[8]_PORT_B_data_in_reg = DFFE(GB4_q_a[8]_PORT_B_data_in, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[8]_PORT_A_address_reg = DFFE(GB4_q_a[8]_PORT_A_address, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[8]_PORT_B_address_reg = DFFE(GB4_q_a[8]_PORT_B_address, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_PORT_A_write_enable = GND;
GB4_q_a[8]_PORT_A_write_enable_reg = DFFE(GB4_q_a[8]_PORT_A_write_enable, GB4_q_a[8]_clock_0, , , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[8]_PORT_B_write_enable_reg = DFFE(GB4_q_a[8]_PORT_B_write_enable, GB4_q_a[8]_clock_1, , , GB4_q_a[8]_clock_enable_1);
GB4_q_a[8]_clock_0 = CCD_MCLK;
GB4_q_a[8]_clock_1 = KB1__clk0;
GB4_q_a[8]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[8]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[8]_clear_1 = !C1_oRST_0;
GB4_q_a[8]_PORT_A_data_out = MEMORY(GB4_q_a[8]_PORT_A_data_in_reg, GB4_q_a[8]_PORT_B_data_in_reg, GB4_q_a[8]_PORT_A_address_reg, GB4_q_a[8]_PORT_B_address_reg, GB4_q_a[8]_PORT_A_write_enable_reg, GB4_q_a[8]_PORT_B_write_enable_reg, , , GB4_q_a[8]_clock_0, GB4_q_a[8]_clock_1, GB4_q_a[8]_clock_enable_0, GB4_q_a[8]_clock_enable_1, , GB4_q_a[8]_clear_1);
GB4_q_a[8]_PORT_A_data_out_reg = DFFE(GB4_q_a[8]_PORT_A_data_out, GB4_q_a[8]_clock_0, GB4_q_a[8]_clear_1, , GB4_q_a[8]_clock_enable_0);
GB4_q_a[8] = GB4_q_a[8]_PORT_A_data_out_reg[0];


--B1L112 is VGA_Controller:u1|oVGA_R[8]~276
B1L112 = GB4_q_a[8] & B1L114 & B1L115;


--GB4_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[9]_PORT_A_data_in = VCC;
GB4_q_a[9]_PORT_A_data_in_reg = DFFE(GB4_q_a[9]_PORT_A_data_in, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_data_in = G1_mDATAOUT[9];
GB4_q_a[9]_PORT_B_data_in_reg = DFFE(GB4_q_a[9]_PORT_B_data_in, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[9]_PORT_A_address_reg = DFFE(GB4_q_a[9]_PORT_A_address, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[9]_PORT_B_address_reg = DFFE(GB4_q_a[9]_PORT_B_address, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_PORT_A_write_enable = GND;
GB4_q_a[9]_PORT_A_write_enable_reg = DFFE(GB4_q_a[9]_PORT_A_write_enable, GB4_q_a[9]_clock_0, , , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[9]_PORT_B_write_enable_reg = DFFE(GB4_q_a[9]_PORT_B_write_enable, GB4_q_a[9]_clock_1, , , GB4_q_a[9]_clock_enable_1);
GB4_q_a[9]_clock_0 = CCD_MCLK;
GB4_q_a[9]_clock_1 = KB1__clk0;
GB4_q_a[9]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[9]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[9]_clear_1 = !C1_oRST_0;
GB4_q_a[9]_PORT_A_data_out = MEMORY(GB4_q_a[9]_PORT_A_data_in_reg, GB4_q_a[9]_PORT_B_data_in_reg, GB4_q_a[9]_PORT_A_address_reg, GB4_q_a[9]_PORT_B_address_reg, GB4_q_a[9]_PORT_A_write_enable_reg, GB4_q_a[9]_PORT_B_write_enable_reg, , , GB4_q_a[9]_clock_0, GB4_q_a[9]_clock_1, GB4_q_a[9]_clock_enable_0, GB4_q_a[9]_clock_enable_1, , GB4_q_a[9]_clear_1);
GB4_q_a[9]_PORT_A_data_out_reg = DFFE(GB4_q_a[9]_PORT_A_data_out, GB4_q_a[9]_clock_0, GB4_q_a[9]_clear_1, , GB4_q_a[9]_clock_enable_0);
GB4_q_a[9] = GB4_q_a[9]_PORT_A_data_out_reg[0];


--B1L113 is VGA_Controller:u1|oVGA_R[9]~277
B1L113 = GB4_q_a[9] & B1L114 & B1L115;


--GB4_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[10]_PORT_A_data_in = VCC;
GB4_q_a[10]_PORT_A_data_in_reg = DFFE(GB4_q_a[10]_PORT_A_data_in, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
GB4_q_a[10]_PORT_B_data_in_reg = DFFE(GB4_q_a[10]_PORT_B_data_in, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[10]_PORT_A_address_reg = DFFE(GB4_q_a[10]_PORT_A_address, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[10]_PORT_B_address_reg = DFFE(GB4_q_a[10]_PORT_B_address, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_PORT_A_write_enable = GND;
GB4_q_a[10]_PORT_A_write_enable_reg = DFFE(GB4_q_a[10]_PORT_A_write_enable, GB4_q_a[10]_clock_0, , , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[10]_PORT_B_write_enable_reg = DFFE(GB4_q_a[10]_PORT_B_write_enable, GB4_q_a[10]_clock_1, , , GB4_q_a[10]_clock_enable_1);
GB4_q_a[10]_clock_0 = CCD_MCLK;
GB4_q_a[10]_clock_1 = KB1__clk0;
GB4_q_a[10]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[10]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[10]_clear_1 = !C1_oRST_0;
GB4_q_a[10]_PORT_A_data_out = MEMORY(GB4_q_a[10]_PORT_A_data_in_reg, GB4_q_a[10]_PORT_B_data_in_reg, GB4_q_a[10]_PORT_A_address_reg, GB4_q_a[10]_PORT_B_address_reg, GB4_q_a[10]_PORT_A_write_enable_reg, GB4_q_a[10]_PORT_B_write_enable_reg, , , GB4_q_a[10]_clock_0, GB4_q_a[10]_clock_1, GB4_q_a[10]_clock_enable_0, GB4_q_a[10]_clock_enable_1, , GB4_q_a[10]_clear_1);
GB4_q_a[10]_PORT_A_data_out_reg = DFFE(GB4_q_a[10]_PORT_A_data_out, GB4_q_a[10]_clock_0, GB4_q_a[10]_clear_1, , GB4_q_a[10]_clock_enable_0);
GB4_q_a[10] = GB4_q_a[10]_PORT_A_data_out_reg[0];


--B1L93 is VGA_Controller:u1|oVGA_G[0]~110
B1L93 = GB4_q_a[10] & B1L114 & B1L115;


--GB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[11]_PORT_A_data_in = VCC;
GB4_q_a[11]_PORT_A_data_in_reg = DFFE(GB4_q_a[11]_PORT_A_data_in, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
GB4_q_a[11]_PORT_B_data_in_reg = DFFE(GB4_q_a[11]_PORT_B_data_in, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[11]_PORT_A_address_reg = DFFE(GB4_q_a[11]_PORT_A_address, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[11]_PORT_B_address_reg = DFFE(GB4_q_a[11]_PORT_B_address, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_PORT_A_write_enable = GND;
GB4_q_a[11]_PORT_A_write_enable_reg = DFFE(GB4_q_a[11]_PORT_A_write_enable, GB4_q_a[11]_clock_0, , , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[11]_PORT_B_write_enable_reg = DFFE(GB4_q_a[11]_PORT_B_write_enable, GB4_q_a[11]_clock_1, , , GB4_q_a[11]_clock_enable_1);
GB4_q_a[11]_clock_0 = CCD_MCLK;
GB4_q_a[11]_clock_1 = KB1__clk0;
GB4_q_a[11]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[11]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[11]_clear_1 = !C1_oRST_0;
GB4_q_a[11]_PORT_A_data_out = MEMORY(GB4_q_a[11]_PORT_A_data_in_reg, GB4_q_a[11]_PORT_B_data_in_reg, GB4_q_a[11]_PORT_A_address_reg, GB4_q_a[11]_PORT_B_address_reg, GB4_q_a[11]_PORT_A_write_enable_reg, GB4_q_a[11]_PORT_B_write_enable_reg, , , GB4_q_a[11]_clock_0, GB4_q_a[11]_clock_1, GB4_q_a[11]_clock_enable_0, GB4_q_a[11]_clock_enable_1, , GB4_q_a[11]_clear_1);
GB4_q_a[11]_PORT_A_data_out_reg = DFFE(GB4_q_a[11]_PORT_A_data_out, GB4_q_a[11]_clock_0, GB4_q_a[11]_clear_1, , GB4_q_a[11]_clock_enable_0);
GB4_q_a[11] = GB4_q_a[11]_PORT_A_data_out_reg[0];


--B1L94 is VGA_Controller:u1|oVGA_G[1]~111
B1L94 = GB4_q_a[11] & B1L114 & B1L115;


--GB4_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[12]_PORT_A_data_in = VCC;
GB4_q_a[12]_PORT_A_data_in_reg = DFFE(GB4_q_a[12]_PORT_A_data_in, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
GB4_q_a[12]_PORT_B_data_in_reg = DFFE(GB4_q_a[12]_PORT_B_data_in, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[12]_PORT_A_address_reg = DFFE(GB4_q_a[12]_PORT_A_address, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[12]_PORT_B_address_reg = DFFE(GB4_q_a[12]_PORT_B_address, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_PORT_A_write_enable = GND;
GB4_q_a[12]_PORT_A_write_enable_reg = DFFE(GB4_q_a[12]_PORT_A_write_enable, GB4_q_a[12]_clock_0, , , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[12]_PORT_B_write_enable_reg = DFFE(GB4_q_a[12]_PORT_B_write_enable, GB4_q_a[12]_clock_1, , , GB4_q_a[12]_clock_enable_1);
GB4_q_a[12]_clock_0 = CCD_MCLK;
GB4_q_a[12]_clock_1 = KB1__clk0;
GB4_q_a[12]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[12]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[12]_clear_1 = !C1_oRST_0;
GB4_q_a[12]_PORT_A_data_out = MEMORY(GB4_q_a[12]_PORT_A_data_in_reg, GB4_q_a[12]_PORT_B_data_in_reg, GB4_q_a[12]_PORT_A_address_reg, GB4_q_a[12]_PORT_B_address_reg, GB4_q_a[12]_PORT_A_write_enable_reg, GB4_q_a[12]_PORT_B_write_enable_reg, , , GB4_q_a[12]_clock_0, GB4_q_a[12]_clock_1, GB4_q_a[12]_clock_enable_0, GB4_q_a[12]_clock_enable_1, , GB4_q_a[12]_clear_1);
GB4_q_a[12]_PORT_A_data_out_reg = DFFE(GB4_q_a[12]_PORT_A_data_out, GB4_q_a[12]_clock_0, GB4_q_a[12]_clear_1, , GB4_q_a[12]_clock_enable_0);
GB4_q_a[12] = GB4_q_a[12]_PORT_A_data_out_reg[0];


--B1L95 is VGA_Controller:u1|oVGA_G[2]~112
B1L95 = GB4_q_a[12] & B1L114 & B1L115;


--GB4_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[13]_PORT_A_data_in = VCC;
GB4_q_a[13]_PORT_A_data_in_reg = DFFE(GB4_q_a[13]_PORT_A_data_in, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
GB4_q_a[13]_PORT_B_data_in_reg = DFFE(GB4_q_a[13]_PORT_B_data_in, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[13]_PORT_A_address_reg = DFFE(GB4_q_a[13]_PORT_A_address, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[13]_PORT_B_address_reg = DFFE(GB4_q_a[13]_PORT_B_address, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_PORT_A_write_enable = GND;
GB4_q_a[13]_PORT_A_write_enable_reg = DFFE(GB4_q_a[13]_PORT_A_write_enable, GB4_q_a[13]_clock_0, , , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[13]_PORT_B_write_enable_reg = DFFE(GB4_q_a[13]_PORT_B_write_enable, GB4_q_a[13]_clock_1, , , GB4_q_a[13]_clock_enable_1);
GB4_q_a[13]_clock_0 = CCD_MCLK;
GB4_q_a[13]_clock_1 = KB1__clk0;
GB4_q_a[13]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[13]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[13]_clear_1 = !C1_oRST_0;
GB4_q_a[13]_PORT_A_data_out = MEMORY(GB4_q_a[13]_PORT_A_data_in_reg, GB4_q_a[13]_PORT_B_data_in_reg, GB4_q_a[13]_PORT_A_address_reg, GB4_q_a[13]_PORT_B_address_reg, GB4_q_a[13]_PORT_A_write_enable_reg, GB4_q_a[13]_PORT_B_write_enable_reg, , , GB4_q_a[13]_clock_0, GB4_q_a[13]_clock_1, GB4_q_a[13]_clock_enable_0, GB4_q_a[13]_clock_enable_1, , GB4_q_a[13]_clear_1);
GB4_q_a[13]_PORT_A_data_out_reg = DFFE(GB4_q_a[13]_PORT_A_data_out, GB4_q_a[13]_clock_0, GB4_q_a[13]_clear_1, , GB4_q_a[13]_clock_enable_0);
GB4_q_a[13] = GB4_q_a[13]_PORT_A_data_out_reg[0];


--B1L96 is VGA_Controller:u1|oVGA_G[3]~113
B1L96 = GB4_q_a[13] & B1L114 & B1L115;


--GB4_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[14]_PORT_A_data_in = VCC;
GB4_q_a[14]_PORT_A_data_in_reg = DFFE(GB4_q_a[14]_PORT_A_data_in, GB4_q_a[14]_clock_0, , , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
GB4_q_a[14]_PORT_B_data_in_reg = DFFE(GB4_q_a[14]_PORT_B_data_in, GB4_q_a[14]_clock_1, , , GB4_q_a[14]_clock_enable_1);
GB4_q_a[14]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[14]_PORT_A_address_reg = DFFE(GB4_q_a[14]_PORT_A_address, GB4_q_a[14]_clock_0, , , GB4_q_a[14]_clock_enable_0);
GB4_q_a[14]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[14]_PORT_B_address_reg = DFFE(GB4_q_a[14]_PORT_B_address, GB4_q_a[14]_clock_1, , , GB4_q_a[14]_clock_enable_1);
GB4_q_a[14]_P