de2_ccd.map.eqn

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

GB4_q_a[1]_PORT_A_data_in = VCC;
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = G1_mDATAOUT[1];
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = CCD_MCLK;
GB4_q_a[1]_clock_1 = KB1__clk0;
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !C1_oRST_0;
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1] = GB4_q_a[1]_PORT_A_data_out_reg[0];


--B1L105 is VGA_Controller:u1|oVGA_R[1]~269
B1L105 = GB4_q_a[1] & B1L114 & B1L115;


--GB4_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[2]_PORT_A_data_in = VCC;
GB4_q_a[2]_PORT_A_data_in_reg = DFFE(GB4_q_a[2]_PORT_A_data_in, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_data_in = G1_mDATAOUT[2];
GB4_q_a[2]_PORT_B_data_in_reg = DFFE(GB4_q_a[2]_PORT_B_data_in, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[2]_PORT_A_address_reg = DFFE(GB4_q_a[2]_PORT_A_address, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[2]_PORT_B_address_reg = DFFE(GB4_q_a[2]_PORT_B_address, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_PORT_A_write_enable = GND;
GB4_q_a[2]_PORT_A_write_enable_reg = DFFE(GB4_q_a[2]_PORT_A_write_enable, GB4_q_a[2]_clock_0, , , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[2]_PORT_B_write_enable_reg = DFFE(GB4_q_a[2]_PORT_B_write_enable, GB4_q_a[2]_clock_1, , , GB4_q_a[2]_clock_enable_1);
GB4_q_a[2]_clock_0 = CCD_MCLK;
GB4_q_a[2]_clock_1 = KB1__clk0;
GB4_q_a[2]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[2]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[2]_clear_1 = !C1_oRST_0;
GB4_q_a[2]_PORT_A_data_out = MEMORY(GB4_q_a[2]_PORT_A_data_in_reg, GB4_q_a[2]_PORT_B_data_in_reg, GB4_q_a[2]_PORT_A_address_reg, GB4_q_a[2]_PORT_B_address_reg, GB4_q_a[2]_PORT_A_write_enable_reg, GB4_q_a[2]_PORT_B_write_enable_reg, , , GB4_q_a[2]_clock_0, GB4_q_a[2]_clock_1, GB4_q_a[2]_clock_enable_0, GB4_q_a[2]_clock_enable_1, , GB4_q_a[2]_clear_1);
GB4_q_a[2]_PORT_A_data_out_reg = DFFE(GB4_q_a[2]_PORT_A_data_out, GB4_q_a[2]_clock_0, GB4_q_a[2]_clear_1, , GB4_q_a[2]_clock_enable_0);
GB4_q_a[2] = GB4_q_a[2]_PORT_A_data_out_reg[0];


--B1L106 is VGA_Controller:u1|oVGA_R[2]~270
B1L106 = GB4_q_a[2] & B1L114 & B1L115;


--GB4_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[3]_PORT_A_data_in = VCC;
GB4_q_a[3]_PORT_A_data_in_reg = DFFE(GB4_q_a[3]_PORT_A_data_in, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_data_in = G1_mDATAOUT[3];
GB4_q_a[3]_PORT_B_data_in_reg = DFFE(GB4_q_a[3]_PORT_B_data_in, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[3]_PORT_A_address_reg = DFFE(GB4_q_a[3]_PORT_A_address, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[3]_PORT_B_address_reg = DFFE(GB4_q_a[3]_PORT_B_address, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_PORT_A_write_enable = GND;
GB4_q_a[3]_PORT_A_write_enable_reg = DFFE(GB4_q_a[3]_PORT_A_write_enable, GB4_q_a[3]_clock_0, , , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[3]_PORT_B_write_enable_reg = DFFE(GB4_q_a[3]_PORT_B_write_enable, GB4_q_a[3]_clock_1, , , GB4_q_a[3]_clock_enable_1);
GB4_q_a[3]_clock_0 = CCD_MCLK;
GB4_q_a[3]_clock_1 = KB1__clk0;
GB4_q_a[3]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[3]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[3]_clear_1 = !C1_oRST_0;
GB4_q_a[3]_PORT_A_data_out = MEMORY(GB4_q_a[3]_PORT_A_data_in_reg, GB4_q_a[3]_PORT_B_data_in_reg, GB4_q_a[3]_PORT_A_address_reg, GB4_q_a[3]_PORT_B_address_reg, GB4_q_a[3]_PORT_A_write_enable_reg, GB4_q_a[3]_PORT_B_write_enable_reg, , , GB4_q_a[3]_clock_0, GB4_q_a[3]_clock_1, GB4_q_a[3]_clock_enable_0, GB4_q_a[3]_clock_enable_1, , GB4_q_a[3]_clear_1);
GB4_q_a[3]_PORT_A_data_out_reg = DFFE(GB4_q_a[3]_PORT_A_data_out, GB4_q_a[3]_clock_0, GB4_q_a[3]_clear_1, , GB4_q_a[3]_clock_enable_0);
GB4_q_a[3] = GB4_q_a[3]_PORT_A_data_out_reg[0];


--B1L107 is VGA_Controller:u1|oVGA_R[3]~271
B1L107 = GB4_q_a[3] & B1L114 & B1L115;


--GB4_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[4]_PORT_A_data_in = VCC;
GB4_q_a[4]_PORT_A_data_in_reg = DFFE(GB4_q_a[4]_PORT_A_data_in, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_data_in = G1_mDATAOUT[4];
GB4_q_a[4]_PORT_B_data_in_reg = DFFE(GB4_q_a[4]_PORT_B_data_in, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[4]_PORT_A_address_reg = DFFE(GB4_q_a[4]_PORT_A_address, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[4]_PORT_B_address_reg = DFFE(GB4_q_a[4]_PORT_B_address, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_PORT_A_write_enable = GND;
GB4_q_a[4]_PORT_A_write_enable_reg = DFFE(GB4_q_a[4]_PORT_A_write_enable, GB4_q_a[4]_clock_0, , , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[4]_PORT_B_write_enable_reg = DFFE(GB4_q_a[4]_PORT_B_write_enable, GB4_q_a[4]_clock_1, , , GB4_q_a[4]_clock_enable_1);
GB4_q_a[4]_clock_0 = CCD_MCLK;
GB4_q_a[4]_clock_1 = KB1__clk0;
GB4_q_a[4]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[4]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[4]_clear_1 = !C1_oRST_0;
GB4_q_a[4]_PORT_A_data_out = MEMORY(GB4_q_a[4]_PORT_A_data_in_reg, GB4_q_a[4]_PORT_B_data_in_reg, GB4_q_a[4]_PORT_A_address_reg, GB4_q_a[4]_PORT_B_address_reg, GB4_q_a[4]_PORT_A_write_enable_reg, GB4_q_a[4]_PORT_B_write_enable_reg, , , GB4_q_a[4]_clock_0, GB4_q_a[4]_clock_1, GB4_q_a[4]_clock_enable_0, GB4_q_a[4]_clock_enable_1, , GB4_q_a[4]_clear_1);
GB4_q_a[4]_PORT_A_data_out_reg = DFFE(GB4_q_a[4]_PORT_A_data_out, GB4_q_a[4]_clock_0, GB4_q_a[4]_clear_1, , GB4_q_a[4]_clock_enable_0);
GB4_q_a[4] = GB4_q_a[4]_PORT_A_data_out_reg[0];


--B1L108 is VGA_Controller:u1|oVGA_R[4]~272
B1L108 = GB4_q_a[4] & B1L114 & B1L115;


--GB4_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[5]_PORT_A_data_in = VCC;
GB4_q_a[5]_PORT_A_data_in_reg = DFFE(GB4_q_a[5]_PORT_A_data_in, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
GB4_q_a[5]_PORT_B_data_in_reg = DFFE(GB4_q_a[5]_PORT_B_data_in, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[5]_PORT_A_address_reg = DFFE(GB4_q_a[5]_PORT_A_address, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[5]_PORT_B_address_reg = DFFE(GB4_q_a[5]_PORT_B_address, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_PORT_A_write_enable = GND;
GB4_q_a[5]_PORT_A_write_enable_reg = DFFE(GB4_q_a[5]_PORT_A_write_enable, GB4_q_a[5]_clock_0, , , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[5]_PORT_B_write_enable_reg = DFFE(GB4_q_a[5]_PORT_B_write_enable, GB4_q_a[5]_clock_1, , , GB4_q_a[5]_clock_enable_1);
GB4_q_a[5]_clock_0 = CCD_MCLK;
GB4_q_a[5]_clock_1 = KB1__clk0;
GB4_q_a[5]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[5]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[5]_clear_1 = !C1_oRST_0;
GB4_q_a[5]_PORT_A_data_out = MEMORY(GB4_q_a[5]_PORT_A_data_in_reg, GB4_q_a[5]_PORT_B_data_in_reg, GB4_q_a[5]_PORT_A_address_reg, GB4_q_a[5]_PORT_B_address_reg, GB4_q_a[5]_PORT_A_write_enable_reg, GB4_q_a[5]_PORT_B_write_enable_reg, , , GB4_q_a[5]_clock_0, GB4_q_a[5]_clock_1, GB4_q_a[5]_clock_enable_0, GB4_q_a[5]_clock_enable_1, , GB4_q_a[5]_clear_1);
GB4_q_a[5]_PORT_A_data_out_reg = DFFE(GB4_q_a[5]_PORT_A_data_out, GB4_q_a[5]_clock_0, GB4_q_a[5]_clear_1, , GB4_q_a[5]_clock_enable_0);
GB4_q_a[5] = GB4_q_a[5]_PORT_A_data_out_reg[0];


--B1L109 is VGA_Controller:u1|oVGA_R[5]~273
B1L109 = GB4_q_a[5] & B1L114 & B1L115;


--GB4_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[6]_PORT_A_data_in = VCC;
GB4_q_a[6]_PORT_A_data_in_reg = DFFE(GB4_q_a[6]_PORT_A_data_in, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
GB4_q_a[6]_PORT_B_data_in_reg = DFFE(GB4_q_a[6]_PORT_B_data_in, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[6]_PORT_A_address_reg = DFFE(GB4_q_a[6]_PORT_A_address, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[6]_PORT_B_address_reg = DFFE(GB4_q_a[6]_PORT_B_address, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_PORT_A_write_enable = GND;
GB4_q_a[6]_PORT_A_write_enable_reg = DFFE(GB4_q_a[6]_PORT_A_write_enable, GB4_q_a[6]_clock_0, , , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[6]_PORT_B_write_enable_reg = DFFE(GB4_q_a[6]_PORT_B_write_enable, GB4_q_a[6]_clock_1, , , GB4_q_a[6]_clock_enable_1);
GB4_q_a[6]_clock_0 = CCD_MCLK;
GB4_q_a[6]_clock_1 = KB1__clk0;
GB4_q_a[6]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[6]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[6]_clear_1 = !C1_oRST_0;
GB4_q_a[6]_PORT_A_data_out = MEMORY(GB4_q_a[6]_PORT_A_data_in_reg, GB4_q_a[6]_PORT_B_data_in_reg, GB4_q_a[6]_PORT_A_address_reg, GB4_q_a[6]_PORT_B_address_reg, GB4_q_a[6]_PORT_A_write_enable_reg, GB4_q_a[6]_PORT_B_write_enable_reg, , , GB4_q_a[6]_clock_0, GB4_q_a[6]_clock_1, GB4_q_a[6]_clock_enable_0, GB4_q_a[6]_clock_enable_1, , GB4_q_a[6]_clear_1);
GB4_q_a[6]_PORT_A_data_out_reg = DFFE(GB4_q_a[6]_PORT_A_data_out, GB4_q_a[6]_clock_0, GB4_q_a[6]_clear_1, , GB4_q_a[6]_clock_enable_0);
GB4_q_a[6] = GB4_q_a[6]_PORT_A_data_out_reg[0];


--B1L110 is VGA_Controller:u1|oVGA_R[6]~274
B1L110 = GB4_q_a[6] & B1L114 & B1L115;


--GB4_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[7]_PORT_A_data_in = VCC;
GB4_q_a[7]_PORT_A_data_in_reg = DFFE(GB4_q_a[7]_PORT_A_data_in, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_data_in = G1_mDATAOUT[7];
GB4_q_a[7]_PORT_B_data_in_reg = DFFE(GB4_q_a[7]_PORT_B_data_in, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[7]_PORT_A_address_reg = DFFE(GB4_q_a[7]_PORT_A_address, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[7]_PORT_B_address_reg = DFFE(GB4_q_a[7]_PORT_B_address, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_PORT_A_write_enable = GND;
GB4_q_a[7]_PORT_A_write_enable_reg = DFFE(GB4_q_a[7]_PORT_A_write_enable, GB4_q_a[7]_clock_0, , , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[7]_PORT_B_write_enable_reg = DFFE(GB4_q_a[7]_PORT_B_write_enable, GB4_q_a[7]_clock_1, , , GB4_q_a[7]_clock_enable_1);
GB4_q_a[7]_clock_0 = CCD_MCLK;
GB4_q_a[7]_clock_1 = KB1__clk0;
GB4_q_a[7]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[7]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[7]_clear_1 = !C1_oRST_0;
GB4_q_a[7]_PORT_A_data_out = MEMORY(GB4_q_a[7]_PORT_A_data_in_reg, GB4_q_a[7]_PORT_B_data_in_reg, GB4_q_a[7]_PORT_A_address_reg, GB4_q_a[7]_PORT_B_address_reg, GB4_q_a[7]_PORT_A_write_enable_reg, GB4_q_a[7]_PORT_B_write_enable_reg, , , GB4_q_a[7]_clock_0, GB4_q_a[7]_clock_1, GB4_q_a[7]_clock_enable_0, GB4_q_a[7]_clock_enable_1, , GB4_q_a[7]_clear_1);
GB4_q_a[7]_PORT_A_data_out_reg = DFFE(GB4_q_a[7]_PORT_A_data_out, GB4_q_a[7]_clock_0, GB4_q_a[7]_clear_1, , GB4_q_a[7]_clock_enable_0);
GB4_q_a[7] = GB4_q_a[7]_PORT_A_data_out_reg[0];