de2_ccd.map.eqn

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

--G1_SA[4] is Sdram_Control_4Port:u6|SA[4]
G1_SA[4] = DFFEAS(G1L76, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[5] is Sdram_Control_4Port:u6|SA[5]
G1_SA[5] = DFFEAS(G1L77, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[6] is Sdram_Control_4Port:u6|SA[6]
G1_SA[6] = DFFEAS(G1L78, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[7] is Sdram_Control_4Port:u6|SA[7]
G1_SA[7] = DFFEAS(G1L79, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[8] is Sdram_Control_4Port:u6|SA[8]
G1_SA[8] = DFFEAS(G1L80, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[9] is Sdram_Control_4Port:u6|SA[9]
G1_SA[9] = DFFEAS(G1L81, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[10] is Sdram_Control_4Port:u6|SA[10]
G1_SA[10] = DFFEAS(G1L82, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[11] is Sdram_Control_4Port:u6|SA[11]
G1_SA[11] = DFFEAS(G1L83, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_DQM[1] is Sdram_Control_4Port:u6|DQM[1]
G1_DQM[1] = DFFEAS(G1L14, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_WE_N is Sdram_Control_4Port:u6|WE_N
G1_WE_N = DFFEAS(G1L112, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CAS_N is Sdram_Control_4Port:u6|CAS_N
G1_CAS_N = DFFEAS(G1L5, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_RAS_N is Sdram_Control_4Port:u6|RAS_N
G1_RAS_N = DFFEAS(G1L50, KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0]
G1_CS_N[0] = DFFEAS(R1_CS_N[0], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[0] is Sdram_Control_4Port:u6|BA[0]
G1_BA[0] = DFFEAS(R1_BA[0], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[1] is Sdram_Control_4Port:u6|BA[1]
G1_BA[1] = DFFEAS(R1_BA[1], KB1__clk0,  ,  ,  ,  ,  ,  ,  );


--KB1__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
KB1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--KB1__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1
KB1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--CCD_MCLK is CCD_MCLK
CCD_MCLK = DFFEAS(A1L8, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--B1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC
B1_oVGA_H_SYNC = DFFEAS(B1L42, CCD_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC
B1_oVGA_V_SYNC = DFFEAS(B1L117, CCD_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK
B1_oVGA_BLANK = B1_oVGA_H_SYNC & B1_oVGA_V_SYNC;


--GB4_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[0]_PORT_A_data_in = VCC;
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = G1_mDATAOUT[0];
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = CCD_MCLK;
GB4_q_a[0]_clock_1 = KB1__clk0;
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !C1_oRST_0;
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0] = GB4_q_a[0]_PORT_A_data_out_reg[0];


--B1_V_Cont[6] is VGA_Controller:u1|V_Cont[6]
B1_V_Cont[6] = DFFEAS(B1L68, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[7] is VGA_Controller:u1|V_Cont[7]
B1_V_Cont[7] = DFFEAS(B1L71, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[8] is VGA_Controller:u1|V_Cont[8]
B1_V_Cont[8] = DFFEAS(B1L74, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L38 is VGA_Controller:u1|LessThan~1087
B1L38 = !B1_V_Cont[6] & !B1_V_Cont[7] & !B1_V_Cont[8];


--B1_V_Cont[1] is VGA_Controller:u1|V_Cont[1]
B1_V_Cont[1] = DFFEAS(B1L53, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[2] is VGA_Controller:u1|V_Cont[2]
B1_V_Cont[2] = DFFEAS(B1L56, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[3] is VGA_Controller:u1|V_Cont[3]
B1_V_Cont[3] = DFFEAS(B1L59, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L39 is VGA_Controller:u1|LessThan~1088
B1L39 = !B1_V_Cont[1] & !B1_V_Cont[2] & !B1_V_Cont[3];


--B1_V_Cont[4] is VGA_Controller:u1|V_Cont[4]
B1_V_Cont[4] = DFFEAS(B1L62, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[5] is VGA_Controller:u1|V_Cont[5]
B1_V_Cont[5] = DFFEAS(B1L65, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L40 is VGA_Controller:u1|LessThan~1089
B1L40 = B1L39 & !B1_V_Cont[4] # !B1_V_Cont[5];


--B1_V_Cont[9] is VGA_Controller:u1|V_Cont[9]
B1_V_Cont[9] = DFFEAS(B1L77, CCD_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L45,  );


--B1L41 is VGA_Controller:u1|LessThan~1090
B1L41 = B1_V_Cont[4] # B1_V_Cont[5] # !B1L39 # !B1L38;


--B1L114 is VGA_Controller:u1|oVGA_R~266
B1L114 = B1_V_Cont[9] & (!B1L41) # !B1_V_Cont[9] & (!B1L40 # !B1L38);


--B1_H_Cont[4] is VGA_Controller:u1|H_Cont[4]
B1_H_Cont[4] = DFFEAS(B1L20, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[5] is VGA_Controller:u1|H_Cont[5]
B1_H_Cont[5] = DFFEAS(B1L23, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[6] is VGA_Controller:u1|H_Cont[6]
B1_H_Cont[6] = DFFEAS(B1L27, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L1 is VGA_Controller:u1|Equal~115
B1L1 = !B1_H_Cont[4] & !B1_H_Cont[5] & !B1_H_Cont[6];


--B1_H_Cont[7] is VGA_Controller:u1|H_Cont[7]
B1_H_Cont[7] = DFFEAS(B1L30, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[8] is VGA_Controller:u1|H_Cont[8]
B1_H_Cont[8] = DFFEAS(B1L33, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1_H_Cont[9] is VGA_Controller:u1|H_Cont[9]
B1_H_Cont[9] = DFFEAS(B1L36, CCD_MCLK, C1_oRST_2,  ,  ,  ,  , B1L46,  );


--B1L115 is VGA_Controller:u1|oVGA_R~267
B1L115 = B1_H_Cont[8] & (B1L1 & !B1_H_Cont[7] # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # !B1L1 & B1_H_Cont[7]);


--B1L104 is VGA_Controller:u1|oVGA_R[0]~268
B1L104 = GB4_q_a[0] & B1L114 & B1L115;


--GB4_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered