de2_ccd.tan.summary

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.049 ns
From           : DRAM_DQ[1]
To             : Sdram_Control_4Port:u6|mDATAOUT[1]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.054 ns
From           : VGA_Controller:u1|V_Cont[8]
To             : VGA_R[0]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.816 ns
From           : SW[15]
To             : LEDR[15]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.712 ns
From           : SW[0]
To             : I2C_CCD_Config:u7|mI2C_DATA[0]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 3.159 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 146.18 MHz ( period = 6.841 ns )
From           : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]
To             : Sdram_Control_4Port:u6|mADDR[12]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 14.551 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 183.52 MHz ( period = 5.449 ns )
From           : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]
To             : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'GPIO_1[10]'
Slack          : 32.672 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 136.46 MHz ( period = 7.328 ns )
From           : CCD_Capture:u3|X_Cont[0]
To             : RAW2RGB:u4|mCCD_G[10]
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : Sdram_Control_4Port:u6|ST[0]
To             : Sdram_Control_4Port:u6|ST[0]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'GPIO_1[10]'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CCD_Capture:u3|mSTART
To             : CCD_Capture:u3|mSTART
From Clock     : GPIO_1[10]
To Clock       : GPIO_1[10]
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : Reset_Delay:u2|oRST_1
To             : Reset_Delay:u2|oRST_1
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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