de2_ccd.tan.rpt

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

; 3.321 ns                                ; 149.72 MHz ( period = 6.679 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]  ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.449 ns                ;
; 3.321 ns                                ; 149.72 MHz ( period = 6.679 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]  ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.449 ns                ;
; 3.322 ns                                ; 149.75 MHz ( period = 6.678 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.441 ns                ;
; 3.322 ns                                ; 149.75 MHz ( period = 6.678 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.441 ns                ;
; 3.322 ns                                ; 149.75 MHz ( period = 6.678 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.441 ns                ;
; 3.327 ns                                ; 149.86 MHz ( period = 6.673 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[5]  ; Sdram_Control_4Port:u6|WR_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 6.434 ns                ;
; 3.331 ns                                ; 149.95 MHz ( period = 6.669 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]  ; Sdram_Control_4Port:u6|mWR        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.432 ns                ;
; 3.331 ns                                ; 149.95 MHz ( period = 6.669 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]  ; Sdram_Control_4Port:u6|WR_MASK[1] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.432 ns                ;
; 3.333 ns                                ; 149.99 MHz ( period = 6.667 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]  ; Sdram_Control_4Port:u6|WR_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.760 ns                  ; 6.427 ns                ;
; 3.334 ns                                ; 150.02 MHz ( period = 6.666 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.436 ns                ;
; 3.334 ns                                ; 150.02 MHz ( period = 6.666 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.436 ns                ;
; 3.334 ns                                ; 150.02 MHz ( period = 6.666 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.436 ns                ;
; 3.334 ns                                ; 150.02 MHz ( period = 6.666 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.436 ns                ;
; 3.339 ns                                ; 150.13 MHz ( period = 6.661 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]  ; Sdram_Control_4Port:u6|mWR        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 6.425 ns                ;
; 3.339 ns                                ; 150.13 MHz ( period = 6.661 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]  ; Sdram_Control_4Port:u6|WR_MASK[1] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 6.425 ns                ;
; 3.339 ns                                ; 150.13 MHz ( period = 6.661 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.423 ns                ;
; 3.339 ns                                ; 150.13 MHz ( period = 6.661 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.423 ns                ;
; 3.339 ns                                ; 150.13 MHz ( period = 6.661 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.423 ns                ;
; 3.346 ns                                ; 150.29 MHz ( period = 6.654 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[0]  ; Sdram_Control_4Port:u6|WR_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 6.415 ns                ;
; 3.351 ns                                ; 150.40 MHz ( period = 6.649 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.418 ns                ;
; 3.351 ns                                ; 150.40 MHz ( period = 6.649 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.418 ns                ;
; 3.351 ns                                ; 150.40 MHz ( period = 6.649 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.418 ns                ;
; 3.351 ns                                ; 150.40 MHz ( period = 6.649 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.418 ns                ;
; 3.352 ns                                ; 150.42 MHz ( period = 6.648 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|mWR        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 6.412 ns                ;
; 3.352 ns                                ; 150.42 MHz ( period = 6.648 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[6]  ; Sdram_Control_4Port:u6|WR_MASK[1] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 6.412 ns                ;
; 3.368 ns                                ; 150.78 MHz ( period = 6.632 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.394 ns                ;
; 3.368 ns                                ; 150.78 MHz ( period = 6.632 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.394 ns                ;
; 3.368 ns                                ; 150.78 MHz ( period = 6.632 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.394 ns                ;
; 3.369 ns                                ; 150.81 MHz ( period = 6.631 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|mWR        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.394 ns                ;
; 3.369 ns                                ; 150.81 MHz ( period = 6.631 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]  ; Sdram_Control_4Port:u6|WR_MASK[1] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.394 ns                ;
; 3.370 ns                                ; 150.83 MHz ( period = 6.630 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]  ; Sdram_Control_4Port:u6|WR_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.760 ns                  ; 6.390 ns                ;
; 3.378 ns                                ; 151.01 MHz ( period = 6.622 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[0]  ; Sdram_Control_4Port:u6|WR_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 6.383 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mRD        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.382 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|RD_MASK[0] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.382 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|RD_MASK[1] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 6.382 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.389 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.389 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]  ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.769 ns                  ; 6.389 ns                ;
; 3.380 ns                                ; 151.06 MHz ( period = 6.620 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_