de2_ccd.tan.rpt

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

; Ignore Clock Settings                                 ; Off                ;                 ;                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;                 ;                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                         ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                         ;             ;
; Clock Settings                                        ; Ccd Pixclk         ;                 ; GPIO_1[10]              ;             ;
; Clock Settings                                        ; Ccd Mclk           ;                 ; GPIO_1[11]              ;             ;
; Clock Settings                                        ; Ccd Pixclk         ;                 ; GPIO_1[30]              ;             ;
; Clock Settings                                        ; Ccd Mclk           ;                 ; GPIO_1[31]              ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe6|dffe7a ; dcfifo_7lb1 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a ; dcfifo_7lb1 ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -2.368 ns ;              ;
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -5.368 ns ;              ;
; GPIO_1[10]                                                                ; CCD_PIXCLK         ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[30]                                                                ; CCD_PIXCLK         ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[31]                                                                ; CCD_MCLK           ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[11]                                                                ; CCD_MCLK           ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                          ; To                                ; From Clock                                                                ; To Clock                                                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3.159 ns                                ; 146.18 MHz ( period = 6.841 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[12]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.604 ns                ;
; 3.159 ns                                ; 146.18 MHz ( period = 6.841 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[15]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.604 ns                ;
; 3.159 ns                                ; 146.18 MHz ( period = 6.841 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[17]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.604 ns                ;
; 3.171 ns                                ; 146.43 MHz ( period = 6.829 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[18]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.599 ns                ;
; 3.171 ns                                ; 146.43 MHz ( period = 6.829 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[19]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.599 ns                ;
; 3.171 ns                                ; 146.43 MHz ( period = 6.829 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[22]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.599 ns                ;
; 3.171 ns                                ; 146.43 MHz ( period = 6.829 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.770 ns                  ; 6.599 ns                ;
; 3.189 ns                                ; 146.82 MHz ( period = 6.811 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1]  ; Sdram_Control_4Port:u6|mWR        ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 6.575 ns                ;