de2_ccd.tan.rpt

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                                                         ; To                                                                                                                                                           ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                              ; 7.049 ns                         ; DRAM_DQ[1]                                                                                                                   ; Sdram_Control_4Port:u6|mDATAOUT[1]                                                                                                                           ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                              ; 16.054 ns                        ; VGA_Controller:u1|V_Cont[8]                                                                                                  ; VGA_R[0]                                                                                                                                                     ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A       ; None                              ; 9.816 ns                         ; SW[15]                                                                                                                       ; LEDR[15]                                                                                                                                                     ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                              ; 3.712 ns                         ; SW[0]                                                                                                                        ; I2C_CCD_Config:u7|mI2C_DATA[0]                                                                                                                               ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; 3.159 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 146.18 MHz ( period = 6.841 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLOCK_50'                                                                  ; 14.551 ns ; 50.00 MHz ( period = 20.000 ns )  ; 183.52 MHz ( period = 5.449 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[4]                   ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'GPIO_1[10]'                                                                ; 32.672 ns ; 25.00 MHz ( period = 40.000 ns )  ; 136.46 MHz ( period = 7.328 ns ) ; CCD_Capture:u3|X_Cont[0]                                                                                                     ; RAW2RGB:u4|mCCD_G[10]                                                                                                                                        ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; Sdram_Control_4Port:u6|ST[0]                                                                                                 ; Sdram_Control_4Port:u6|ST[0]                                                                                                                                 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'GPIO_1[10]'                                                                 ; 0.391 ns  ; 25.00 MHz ( period = 40.000 ns )  ; N/A                              ; CCD_Capture:u3|mSTART                                                                                                        ; CCD_Capture:u3|mSTART                                                                                                                                        ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; Reset_Delay:u2|oRST_1                                                                                                        ; Reset_Delay:u2|oRST_1                                                                                                                                        ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Total number of failed paths                                                             ;           ;                                   ;                                  ;                                                                                                                              ;                                                                                                                                                              ;                                                                           ;                                                                           ; 0            ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                             ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                      ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;                 ;                         ;             ;
; Timing Models                                         ; Preliminary        ;                 ;                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                         ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                         ;             ;
; Number of paths to report                             ; 200                ;                 ;                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                         ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                         ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;                 ;                         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                         ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                         ;             ;