⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 de2_ccd.fit.eqn

📁 这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头
💻 EQN
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1] = GB4_q_a[1]_PORT_A_data_out_reg[0];

--GB4_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[12] = GB4_q_a[1]_PORT_A_data_out_reg[8];

--GB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[11] = GB4_q_a[1]_PORT_A_data_out_reg[7];

--GB4_q_a[9] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[9] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[9] = GB4_q_a[1]_PORT_A_data_out_reg[6];

--GB4_q_a[7] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[7] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[7] = GB4_q_a[1]_PORT_A_data_out_reg[5];

--GB4_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[6] = GB4_q_a[1]_PORT_A_data_out_reg[4];

--GB4_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[5] = GB4_q_a[1]_PORT_A_data_out_reg[3];

--GB4_q_a[4] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[4] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[1]_PORT_B_address_reg = DFFE(GB4_q_a[1]_PORT_B_address, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_write_enable = GND;
GB4_q_a[1]_PORT_A_write_enable_reg = DFFE(GB4_q_a[1]_PORT_A_write_enable, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[1]_PORT_B_write_enable_reg = DFFE(GB4_q_a[1]_PORT_B_write_enable, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_clock_0 = GLOBAL(A1L9);
GB4_q_a[1]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[1]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[1]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[1]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[1]_PORT_A_data_out = MEMORY(GB4_q_a[1]_PORT_A_data_in_reg, GB4_q_a[1]_PORT_B_data_in_reg, GB4_q_a[1]_PORT_A_address_reg, GB4_q_a[1]_PORT_B_address_reg, GB4_q_a[1]_PORT_A_write_enable_reg, GB4_q_a[1]_PORT_B_write_enable_reg, , , GB4_q_a[1]_clock_0, GB4_q_a[1]_clock_1, GB4_q_a[1]_clock_enable_0, GB4_q_a[1]_clock_enable_1, , GB4_q_a[1]_clear_1);
GB4_q_a[1]_PORT_A_data_out_reg = DFFE(GB4_q_a[1]_PORT_A_data_out, GB4_q_a[1]_clock_0, GB4_q_a[1]_clear_1, , GB4_q_a[1]_clock_enable_0);
GB4_q_a[4] = GB4_q_a[1]_PORT_A_data_out_reg[2];

--GB4_q_a[2] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[2] at M4K_X26_Y17
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);
GB4_q_a[1]_PORT_B_data_in = BUS(G1_mDATAOUT[1], G1_mDATAOUT[2], G1_mDATAOUT[4], G1_mDATAOUT[5], G1_mDATAOUT[6], G1_mDATAOUT[7], G1_mDATAOUT[9], G1_mDATAOUT[11], G1_mDATAOUT[12]);
GB4_q_a[1]_PORT_B_data_in_reg = DFFE(GB4_q_a[1]_PORT_B_data_in, GB4_q_a[1]_clock_1, , , GB4_q_a[1]_clock_enable_1);
GB4_q_a[1]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[1]_PORT_A_address_reg = DFFE(GB4_q_a[1]_PORT_A_address, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -