de2_ccd.fit.eqn

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[13] = GB4_q_a[0]_PORT_A_data_out_reg[4];

--GB4_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[10] = GB4_q_a[0]_PORT_A_data_out_reg[3];

--GB4_q_a[8] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[8] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[8] = GB4_q_a[0]_PORT_A_data_out_reg[2];

--GB4_q_a[3] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[3] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[3] = GB4_q_a[0]_PORT_A_data_out_reg[1];


--B1_V_Cont[6] is VGA_Controller:u1|V_Cont[6] at LCFF_X20_Y35_N13
B1_V_Cont[6] = DFFEAS(B1L68, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[7] is VGA_Controller:u1|V_Cont[7] at LCFF_X20_Y35_N15
B1_V_Cont[7] = DFFEAS(B1L71, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[8] is VGA_Controller:u1|V_Cont[8] at LCFF_X20_Y35_N17
B1_V_Cont[8] = DFFEAS(B1L74, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L38 is VGA_Controller:u1|LessThan~1087 at LCCOMB_X20_Y35_N30
B1L38 = !B1_V_Cont[8] & !B1_V_Cont[7] & !B1_V_Cont[6];


--B1_V_Cont[1] is VGA_Controller:u1|V_Cont[1] at LCFF_X20_Y35_N3
B1_V_Cont[1] = DFFEAS(B1L53, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[2] is VGA_Controller:u1|V_Cont[2] at LCFF_X20_Y35_N5
B1_V_Cont[2] = DFFEAS(B1L56, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[3] is VGA_Controller:u1|V_Cont[3] at LCFF_X20_Y35_N7
B1_V_Cont[3] = DFFEAS(B1L59, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L39 is VGA_Controller:u1|LessThan~1088 at LCCOMB_X20_Y35_N24
B1L39 = !B1_V_Cont[3] & !B1_V_Cont[2] & !B1_V_Cont[1];


--B1_V_Cont[4] is VGA_Controller:u1|V_Cont[4] at LCFF_X20_Y35_N9
B1_V_Cont[4] = DFFEAS(B1L62, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1_V_Cont[5] is VGA_Controller:u1|V_Cont[5] at LCFF_X20_Y35_N11
B1_V_Cont[5] = DFFEAS(B1L65, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L40 is VGA_Controller:u1|LessThan~1089 at LCCOMB_X19_Y35_N2
B1L40 = !B1_V_Cont[4] & B1L39 # !B1_V_Cont[5];


--B1_V_Cont[9] is VGA_Controller:u1|V_Cont[9] at LCFF_X20_Y35_N19
B1_V_Cont[9] = DFFEAS(B1L77, GLOBAL(A1L9), GLOBAL(C1L84),  , B1L5,  ,  , B1L45,  );


--B1L41 is VGA_Controller:u1|LessThan~1090 at LCCOMB_X19_Y35_N10
B1L41 = B1_V_Cont[5] # B1_V_Cont[4] # !B1L39 # !B1L38;


--B1L114 is VGA_Controller:u1|oVGA_R~266 at LCCOMB_X19_Y35_N28
B1L114 = B1_V_Cont[9] & (!B1L41) # !B1_V_Cont[9] & (!B1L40 # !B1L38);


--B1_H_Cont[4] is VGA_Controller:u1|H_Cont[4] at LCFF_X18_Y35_N13
B1_H_Cont[4] = DFFEAS(B1L20, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[5] is VGA_Controller:u1|H_Cont[5] at LCFF_X18_Y35_N15
B1_H_Cont[5] = DFFEAS(B1L23, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[6] is VGA_Controller:u1|H_Cont[6] at LCFF_X18_Y35_N17
B1_H_Cont[6] = DFFEAS(B1L27, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L1 is VGA_Controller:u1|Equal~115 at LCCOMB_X18_Y35_N30
B1L1 = !B1_H_Cont[6] & !B1_H_Cont[5] & !B1_H_Cont[4];


--B1_H_Cont[7] is VGA_Controller:u1|H_Cont[7] at LCFF_X18_Y35_N19
B1_H_Cont[7] = DFFEAS(B1L30, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[8] is VGA_Controller:u1|H_Cont[8] at LCFF_X18_Y35_N21
B1_H_Cont[8] = DFFEAS(B1L33, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1_H_Cont[9] is VGA_Controller:u1|H_Cont[9] at LCFF_X18_Y35_N23
B1_H_Cont[9] = DFFEAS(B1L36, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  , B1L46,  );


--B1L115 is VGA_Controller:u1|oVGA_R~267 at LCCOMB_X19_Y35_N16
B1L115 = B1_H_Cont[8] & (!B1_H_Cont[7] & B1L1 # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # B1_H_Cont[7] & !B1L1);


--B1L104 is VGA_Controller:u1|oVGA_R[0]~268 at LCCOMB_X25_Y25_N22
B1L104 = B1L114 & B1L115 & GB4_q_a[0];


--GB4_q_a[1] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[1] at M4K_X26_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[1]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[1]_PORT_A_data_in_reg = DFFE(GB4_q_a[1]_PORT_A_data_in, GB4_q_a[1]_clock_0, , , GB4_q_a[1]_clock_enable_0);