de2_ccd.fit.eqn

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

--D1_Y_Cont[1] is CCD_Capture:u3|Y_Cont[1] at LCFF_X57_Y1_N13
D1_Y_Cont[1] = DFFEAS(D1L143, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[2] is CCD_Capture:u3|Y_Cont[2] at LCFF_X57_Y1_N15
D1_Y_Cont[2] = DFFEAS(D1L146, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[3] is CCD_Capture:u3|Y_Cont[3] at LCFF_X57_Y1_N17
D1_Y_Cont[3] = DFFEAS(D1L149, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[4] is CCD_Capture:u3|Y_Cont[4] at LCFF_X57_Y1_N19
D1_Y_Cont[4] = DFFEAS(D1L152, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[5] is CCD_Capture:u3|Y_Cont[5] at LCFF_X57_Y1_N21
D1_Y_Cont[5] = DFFEAS(D1L155, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[6] is CCD_Capture:u3|Y_Cont[6] at LCFF_X57_Y1_N23
D1_Y_Cont[6] = DFFEAS(D1L158, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[7] is CCD_Capture:u3|Y_Cont[7] at LCFF_X57_Y1_N25
D1_Y_Cont[7] = DFFEAS(D1L161, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--D1_Y_Cont[8] is CCD_Capture:u3|Y_Cont[8] at LCFF_X57_Y1_N27
D1_Y_Cont[8] = DFFEAS(D1L164, GLOBAL(A1L11), GLOBAL(C1L81),  , D1L166,  ,  , !D1_mCCD_FVAL,  );


--G1_SA[0] is Sdram_Control_4Port:u6|SA[0] at LCFF_X18_Y11_N27
G1_SA[0] = DFFEAS(G1L75, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[1] is Sdram_Control_4Port:u6|SA[1] at LCFF_X18_Y11_N3
G1_SA[1] = DFFEAS(G1L76, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[2] is Sdram_Control_4Port:u6|SA[2] at LCFF_X18_Y11_N5
G1_SA[2] = DFFEAS(G1L77, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[3] is Sdram_Control_4Port:u6|SA[3] at LCFF_X18_Y11_N31
G1_SA[3] = DFFEAS(G1L78, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[4] is Sdram_Control_4Port:u6|SA[4] at LCFF_X18_Y11_N1
G1_SA[4] = DFFEAS(G1L79, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[5] is Sdram_Control_4Port:u6|SA[5] at LCFF_X18_Y11_N9
G1_SA[5] = DFFEAS(G1L80, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[6] is Sdram_Control_4Port:u6|SA[6] at LCFF_X18_Y11_N17
G1_SA[6] = DFFEAS(G1L81, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[7] is Sdram_Control_4Port:u6|SA[7] at LCFF_X18_Y11_N7
G1_SA[7] = DFFEAS(G1L82, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[8] is Sdram_Control_4Port:u6|SA[8] at LCFF_X18_Y11_N21
G1_SA[8] = DFFEAS(G1L83, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[9] is Sdram_Control_4Port:u6|SA[9] at LCFF_X18_Y11_N25
G1_SA[9] = DFFEAS(G1L84, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[10] is Sdram_Control_4Port:u6|SA[10] at LCFF_X19_Y12_N21
G1_SA[10] = DFFEAS(G1L85, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_SA[11] is Sdram_Control_4Port:u6|SA[11] at LCFF_X19_Y10_N23
G1_SA[11] = DFFEAS(G1L86, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_DQM[1] is Sdram_Control_4Port:u6|DQM[1] at LCFF_X19_Y11_N9
G1_DQM[1] = DFFEAS(G1L17, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_WE_N is Sdram_Control_4Port:u6|WE_N at LCFF_X19_Y10_N17
G1_WE_N = DFFEAS(G1L115, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_CAS_N is Sdram_Control_4Port:u6|CAS_N at LCFF_X19_Y10_N27
G1_CAS_N = DFFEAS(G1L7, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_RAS_N is Sdram_Control_4Port:u6|RAS_N at LCFF_X19_Y10_N15
G1_RAS_N = DFFEAS(G1L53, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0] at LCFF_X19_Y10_N5
G1_CS_N[0] = DFFEAS(G1L14, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_BA[0] is Sdram_Control_4Port:u6|BA[0] at LCFF_X20_Y12_N7
G1_BA[0] = DFFEAS(G1L3, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--G1_BA[1] is Sdram_Control_4Port:u6|BA[1] at LCFF_X19_Y12_N23
G1_BA[1] = DFFEAS(G1L5, GLOBAL(KB1L2),  ,  ,  ,  ,  ,  ,  );


--KB1__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 at PLL_1
KB1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--KB1__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 at PLL_1
KB1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--CCD_MCLK is CCD_MCLK at LCFF_X58_Y32_N15
CCD_MCLK = DFFEAS(A1L8, GLOBAL(A1L15),  ,  ,  ,  ,  ,  ,  );


--B1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC at LCFF_X19_Y35_N1
B1_oVGA_H_SYNC = DFFEAS(B1L42, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  ,  ,  );


--B1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC at LCFF_X19_Y35_N27
B1_oVGA_V_SYNC = DFFEAS(B1L117, GLOBAL(A1L9), GLOBAL(C1L84),  ,  ,  ,  ,  ,  );


--B1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK at LCCOMB_X19_Y35_N18
B1_oVGA_BLANK = B1_oVGA_V_SYNC & B1_oVGA_H_SYNC;


--GB4_q_a[0] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[0] at M4K_X26_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 6, Port B Depth: 512, Port B Width: 6
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0] = GB4_q_a[0]_PORT_A_data_out_reg[0];

--GB4_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);
GB4_q_a[0]_PORT_B_data_in_reg = DFFE(GB4_q_a[0]_PORT_B_data_in, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_address = BUS(Z4_power_modified_counter_values[0], Z4_power_modified_counter_values[1], Z4_power_modified_counter_values[2], Z4_power_modified_counter_values[3], Z4_power_modified_counter_values[4], Z4_power_modified_counter_values[5], Z4_power_modified_counter_values[6], Z4_power_modified_counter_values[7], Z4_power_modified_counter_values[8]);
GB4_q_a[0]_PORT_A_address_reg = DFFE(GB4_q_a[0]_PORT_A_address, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_address = BUS(X4_wrptr_g[0], X4_wrptr_g[1], X4_wrptr_g[2], X4_wrptr_g[3], X4_wrptr_g[4], X4_wrptr_g[5], X4_wrptr_g[6], X4_wrptr_g[7], X4_wrptr_g[8]);
GB4_q_a[0]_PORT_B_address_reg = DFFE(GB4_q_a[0]_PORT_B_address, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_PORT_A_write_enable = GND;
GB4_q_a[0]_PORT_A_write_enable_reg = DFFE(GB4_q_a[0]_PORT_A_write_enable, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_write_enable = X4_valid_wrreq;
GB4_q_a[0]_PORT_B_write_enable_reg = DFFE(GB4_q_a[0]_PORT_B_write_enable, GB4_q_a[0]_clock_1, , , GB4_q_a[0]_clock_enable_1);
GB4_q_a[0]_clock_0 = GLOBAL(A1L9);
GB4_q_a[0]_clock_1 = GLOBAL(KB1L2);
GB4_q_a[0]_clock_enable_0 = X4_valid_rdreq;
GB4_q_a[0]_clock_enable_1 = X4_valid_wrreq;
GB4_q_a[0]_clear_1 = !GLOBAL(C1L78);
GB4_q_a[0]_PORT_A_data_out = MEMORY(GB4_q_a[0]_PORT_A_data_in_reg, GB4_q_a[0]_PORT_B_data_in_reg, GB4_q_a[0]_PORT_A_address_reg, GB4_q_a[0]_PORT_B_address_reg, GB4_q_a[0]_PORT_A_write_enable_reg, GB4_q_a[0]_PORT_B_write_enable_reg, , , GB4_q_a[0]_clock_0, GB4_q_a[0]_clock_1, GB4_q_a[0]_clock_enable_0, GB4_q_a[0]_clock_enable_1, , GB4_q_a[0]_clear_1);
GB4_q_a[0]_PORT_A_data_out_reg = DFFE(GB4_q_a[0]_PORT_A_data_out, GB4_q_a[0]_clock_0, GB4_q_a[0]_clear_1, , GB4_q_a[0]_clock_enable_0);
GB4_q_a[14] = GB4_q_a[0]_PORT_A_data_out_reg[5];

--GB4_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13] at M4K_X26_Y16
GB4_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC);
GB4_q_a[0]_PORT_A_data_in_reg = DFFE(GB4_q_a[0]_PORT_A_data_in, GB4_q_a[0]_clock_0, , , GB4_q_a[0]_clock_enable_0);
GB4_q_a[0]_PORT_B_data_in = BUS(G1_mDATAOUT[0], G1_mDATAOUT[3], G1_mDATAOUT[8], G1_mDATAOUT[10], G1_mDATAOUT[13], G1_mDATAOUT[14]);