de2_ccd.map.rpt

这是用于开发带有摄像头的嵌入式系统的一个参考实例。这个工程中是在Altera的DE2开发板上驱动一个Mt9m011的摄像头

 71. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 72. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 73. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 74. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 75. Parameter Settings for User Entity Instance: I2C_CCD_Config:u7
 76. Parameter Settings for User Entity Instance: Mirror_Col:u8|Stack_RAM:comb_29|altsyncram:altsyncram_component
 77. Parameter Settings for User Entity Instance: Mirror_Col:u8|Stack_RAM:comb_63|altsyncram:altsyncram_component
 78. Parameter Settings for User Entity Instance: Mirror_Col:u8|Stack_RAM:comb_97|altsyncram:altsyncram_component
 79. altshift_taps Parameter Settings by Entity Instance
 80. dcfifo Parameter Settings by Entity Instance
 81. Analysis & Synthesis Equations
 82. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Apr 17 19:52:08 2006         ;
; Quartus II Version                 ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_CCD                                       ;
; Top-level Entity Name              ; DE2_CCD                                       ;
; Family                             ; Cyclone II                                    ;
; Total combinational functions      ; 1038                                          ;
; Total registers                    ; 840                                           ;
; Total pins                         ; 425                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 76,504                                        ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_CCD            ; DE2_CCD            ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;