📄 de2_ccd.v
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output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
assign TD_RESET = 1'b1;
// All inout port turn to tri-state
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign OTG_DATA = 16'hzzzz;
assign LCD_DATA = 8'hzz;
assign SD_DAT = 1'bz;
assign I2C_SDAT = 1'bz;
assign ENET_DATA = 16'hzzzz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_BCLK = 1'bz;
// CCD
wire [9:0] CCD_DATA;
wire CCD_SDAT;
wire CCD_SCLK;
wire CCD_FLASH;
wire CCD_FVAL;
wire CCD_LVAL;
wire CCD_PIXCLK;
reg CCD_MCLK; // CCD Master Clock
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
wire VGA_CTRL_CLK;
wire AUD_CTRL_CLK;
wire [9:0] mCCD_DATA;
wire mCCD_DVAL;
wire mCCD_DVAL_d;
wire [10:0] X_Cont;
wire [10:0] Y_Cont;
wire [9:0] X_ADDR;
wire [31:0] Frame_Cont;
wire [9:0] mCCD_R;
wire [9:0] mCCD_G;
wire [9:0] mCCD_B;
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
wire Read;
reg [9:0] rCCD_DATA;
reg rCCD_LVAL;
reg rCCD_FVAL;
wire [9:0] sCCD_R;
wire [9:0] sCCD_G;
wire [9:0] sCCD_B;
wire sCCD_DVAL;
// For Sensor 1
assign CCD_DATA[0] = GPIO_1[0];
assign CCD_DATA[1] = GPIO_1[1];
assign CCD_DATA[2] = GPIO_1[5];
assign CCD_DATA[3] = GPIO_1[3];
assign CCD_DATA[4] = GPIO_1[2];
assign CCD_DATA[5] = GPIO_1[4];
assign CCD_DATA[6] = GPIO_1[6];
assign CCD_DATA[7] = GPIO_1[7];
assign CCD_DATA[8] = GPIO_1[8];
assign CCD_DATA[9] = GPIO_1[9];
assign GPIO_1[11] = CCD_MCLK;
assign GPIO_1[15] = CCD_SDAT;
assign GPIO_1[14] = CCD_SCLK;
assign CCD_FVAL = GPIO_1[13];
assign CCD_LVAL = GPIO_1[12];
assign CCD_PIXCLK = GPIO_1[10];
// For Sensor 2
/*
assign CCD_DATA[0] = GPIO_1[0+20];
assign CCD_DATA[1] = GPIO_1[1+20];
assign CCD_DATA[2] = GPIO_1[5+20];
assign CCD_DATA[3] = GPIO_1[3+20];
assign CCD_DATA[4] = GPIO_1[2+20];
assign CCD_DATA[5] = GPIO_1[4+20];
assign CCD_DATA[6] = GPIO_1[6+20];
assign CCD_DATA[7] = GPIO_1[7+20];
assign CCD_DATA[8] = GPIO_1[8+20];
assign CCD_DATA[9] = GPIO_1[9+20];
assign GPIO_1[11+20] = CCD_MCLK;
assign GPIO_1[15+20] = CCD_SDAT;
assign GPIO_1[14+20] = CCD_SCLK;
assign CCD_FVAL = GPIO_1[13+20];
assign CCD_LVAL = GPIO_1[12+20];
assign CCD_PIXCLK = GPIO_1[10+20];
*/
assign LEDR = SW;
assign LEDG = Y_Cont;
assign VGA_CTRL_CLK= CCD_MCLK;
assign VGA_CLK = ~CCD_MCLK;
always@(posedge CLOCK_50) CCD_MCLK <= ~CCD_MCLK;
always@(posedge CCD_PIXCLK)
begin
rCCD_DATA <= CCD_DATA;
rCCD_LVAL <= CCD_LVAL;
rCCD_FVAL <= CCD_FVAL;
end
VGA_Controller u1 ( // Host Side
.oRequest(Read),
.iRed(Read_DATA2[9:0]),
.iGreen({Read_DATA1[14:10],Read_DATA2[14:10]}),
.iBlue(Read_DATA1[9:0]),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2) );
Reset_Delay u2 ( .iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2) );
CCD_Capture u3 ( .oDATA(mCCD_DATA),
.oDVAL(mCCD_DVAL),
.oX_Cont(X_Cont),
.oY_Cont(Y_Cont),
.oFrame_Cont(Frame_Cont),
.iDATA(rCCD_DATA),
.iFVAL(rCCD_FVAL),
.iLVAL(rCCD_LVAL),
.iSTART(!KEY[3]),
.iEND(!KEY[2]),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1) );
RAW2RGB u4 ( .oRed(mCCD_R),
.oGreen(mCCD_G),
.oBlue(mCCD_B),
.oDVAL(mCCD_DVAL_d),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont),
.iDATA(mCCD_DATA),
.iDVAL(mCCD_DVAL),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1) );
SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG(Frame_Cont) );
Sdram_Control_4Port u6 ( // HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA( {sCCD_G[9:5],
sCCD_B[9:0]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Write Side 2
.WR2_DATA( {sCCD_G[4:0],
sCCD_R[9:0]}),
.WR2(sCCD_DVAL),
.WR2_ADDR(22'h100000),
.WR2_MAX_ADDR(22'h100000+640*512),
.WR2_LENGTH(9'h100),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(22'h100000+640*16),
.RD2_MAX_ADDR(22'h100000+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
I2C_CCD_Config u7 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(CCD_SCLK),
.I2C_SDAT(CCD_SDAT) );
Mirror_Col u8 ( // Input Side
.iCCD_R(mCCD_R),
.iCCD_G(mCCD_G),
.iCCD_B(mCCD_B),
.iCCD_DVAL(mCCD_DVAL_d),
.iCCD_PIXCLK(CCD_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_R(sCCD_R),
.oCCD_G(sCCD_G),
.oCCD_B(sCCD_B),
.oCCD_DVAL(sCCD_DVAL));
endmodule
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