sfr_245.inc

Mitsubishi M30245 SampleCode

ep3il		.equ		ep3i		; low byte
;
;-------------------------------------------------------
;	USB Endpoint 3 OUT FIFO
;-------------------------------------------------------
ep3o		.equ		02eeh
ep3ol		.equ		ep3o		; low byte
;
;-------------------------------------------------------
;	USB Endpoint 4 IN FIFO
;-------------------------------------------------------
ep4i		.equ		02f0h
ep4il		.equ		ep4i		; low byte
;
;-------------------------------------------------------
;	USB Endpoint 4 OUT FIFO
;-------------------------------------------------------
ep4o		.equ		02f2h
ep4ol		.equ		ep4o		; low byte
;
;-------------------------------------------------------
;	Flash Memory Control Register
;-------------------------------------------------------
fmr0		.equ		02f7h
;
fmr00		.btequ		0,fmr0		; RY/BY Status Flag
fmr01		.btequ		1,fmr0		; CPU rewrite mode select bit
fmr02		.btequ		2,fmr0		; Lock bit disable bit
fmr03		.btequ		3,fmr0		; Flash memory reset bit
fmr05		.btequ		5,fmr0		; User ROM area select bit
;
;-------------------------------------------------------
;	SSI0 Mode Register 0
;-------------------------------------------------------
ssi0mr0		.equ		0310h
;
ssien_ssi0	.btequ		0,ssi0mr0	; SSI enable bit
xmten_ssi0	.btequ		1,ssi0mr0	; Transmit enable bit
rxen_ssi0	.btequ		2,ssi0mr0	; Receive enable bit
rfben_ssi0	.btequ		3,ssi0mr0	; Rate feedback counter enable bit
cwid0_ssi0	.btequ		4,ssi0mr0	; Channel width select bit (0)
cwid1_ssi0	.btequ		5,ssi0mr0	; Channel width select bit (1)
rfmt0_ssi0	.btequ		6,ssi0mr0	; Receive data format select bit (0)
rfmt1_ssi0	.btequ		7,ssi0mr0	; Receive data format select bit (1)
;
;-------------------------------------------------------
;	SSI0 Mode Register 1
;-------------------------------------------------------
ssi0mr1		.equ		0311h
;
xmtfmt_ssi0	.btequ		0,ssi0mr1	; Transmit data format select bit
rfbsrc_ssi0	.btequ		2,ssi0mr1	; Rate feedback counter source select bit
sckp_ssi0	.btequ		3,ssi0mr1	; SCK polarity select bit
wsp_ssi0	.btequ		4,ssi0mr1	; WS polarity select bit
wsdly_ssi0	.btequ		5,ssi0mr1	; WS delay select bit
;
;-------------------------------------------------------
;	SSI0 Transmit Buffer Register
;-------------------------------------------------------
ssi0txb		.equ		0314h
;
ssi0txbl	.equ		ssi0txb		; Low byte
;
;-------------------------------------------------------
;	SSI0 Receive Buffer Register
;-------------------------------------------------------
ssi0rxb		.equ		0316h
;
ssi0rxbl	.equ		ssi0rxb		; Low byte
;
;-------------------------------------------------------
;	SSI0 Rate Feedback Register
;-------------------------------------------------------
ssi0rf		.equ		0318h
;
;-------------------------------------------------------
;	UART3 Special Mode Register 4
;-------------------------------------------------------
u3smr4		.equ		0324h
;
stareq_u3	.btequ		0,u3smr4	; Start condition generate bit
rstareq_u3	.btequ		1,u3smr4	; Restart condition generate bit
stpreq_u3	.btequ		2,u3smr4	; Stop condition generate bit
stapsel_u3	.btequ		3,u3smr4	; SCL, SDA output select bit
ackd_u3		.btequ		4,u3smr4	; ACK data bit
ackc_u3		.btequ		5,u3smr4	; ACK data output enable bit
sclhi_u3	.btequ		6,u3smr4	; SCL output stop enable bit
swc9_u3		.btequ		7,u3smr4	; SCL wait output bit 3
;
;-------------------------------------------------------
;	UART3 Special Mode Register 3
;-------------------------------------------------------
u3smr3		.equ		0325h
;
sse_u3		.btequ		0,u3smr3	; /SS port function enable bit
ckph_u3		.btequ		1,u3smr3	; Clock phase set bit
dinc_u3		.btequ		2,u3smr3	; Serial input port set bit
nodc_u3		.btequ		3,u3smr3	; Clock output select bit
err_u3		.btequ		4,u3smr3	; Fault error flag
dl0_u3		.btequ		5,u3smr3	; SDA3 digital delay time set bit 0
dl1_u3		.btequ		6,u3smr3	; SDA3 digital delay time set bit 1
dl2_u3		.btequ		7,u3smr3	; SDA3 digital delay time set bit 2
;
;-------------------------------------------------------
;	UART3 Special Mode Register 2
;-------------------------------------------------------
u3smr2		.equ		0326h
;
iicm2_u3	.btequ		0,u3smr2	; IIC mode select bit 2
csc_u3		.btequ		1,u3smr2	; Clock synchronous bit
swc_u3		.btequ		2,u3smr2	; SCL wait output bit
als_u3		.btequ		3,u3smr2	; SDA output stop bit
stc_u3		.btequ		4,u3smr2	; UART3 initialize bit
swc2_u3		.btequ		5,u3smr2	; SCL wait output bit 2
sdhi_u3		.btequ		6,u3smr2	; SDA output inhibit bit
sclkdiv_u3	.btequ		7,u3smr2	; Clock divide set bit
;
;-------------------------------------------------------
;	UART3 Special Mode Register
;-------------------------------------------------------
u3smr		.equ		0327h
;
iicm_u3		.btequ		0,u3smr		; IIC mode select bit
abc_u3		.btequ		1,u3smr		; Arbitration lost detecting flag control bit
bbs_u3		.btequ		2,u3smr		; Bus busy flag
lsyn_u3		.btequ		3,u3smr		; SCLL sync output enable bit
abscs_u3	.btequ		4,u3smr		; Bus collision detect sampling clock select bit
acse_u3		.btequ		5,u3smr		; Auto-clear func select bit of tx enable bit
sss_u3		.btequ		6,u3smr		; Tx start condition select bit
su1him_u3	.btequ		7,u3smr		; clock divide synch enable bit
;
;-------------------------------------------------------
;	UART3 Transmit/Receive Mode Register
;-------------------------------------------------------
u3mr		.equ		0328h
;
smd0_u3		.btequ		0,u3mr		; Serial I/O mode select bit 0
smd1_u3		.btequ		1,u3mr		; Serial I/O mode select bit 1
smd2_u3		.btequ		2,u3mr		; Serial I/O mode select bit 2
ckdir_u3	.btequ		3,u3mr		; Internal/external clock select bit
stps_u3		.btequ		4,u3mr		; Stop bit length select bit
pry_u3		.btequ		5,u3mr		; Odd/even parity select bit
prye_u3		.btequ		6,u3mr		; Parity enable bit
iopol_u3	.btequ		7,u3mr		; Tx,Rx input/output polarity switch bit
;
;-------------------------------------------------------
;	UART3 Bit Rate Generator
;-------------------------------------------------------
u3brg		.equ		0329h
;
;-------------------------------------------------------
;	UART3 Transmit Buffer Register
;-------------------------------------------------------
u3tb		.equ		032ah
;
u3tbl		.equ		u3tb		; UART3 transmit buffer low
u3tbh		.equ		u3tb+1		; UART3 transmit buffer high
;
;-------------------------------------------------------
;	UART3 Transmit/Receive Control Register	0
;-------------------------------------------------------
u3c0		.equ		032ch
;
clk0_u3		.btequ		0,u3c0		; Brg count source select bit 0
clk1_u3		.btequ		1,u3c0		; Brg count source select bit 1
crs_u3		.btequ		2,u3c0		; Cts/rts function select bit
txept_u3	.btequ		3,u3c0		; Transmit register empty flag
crd_u3		.btequ		4,u3c0		; Cts/rts disable bit
nch_u3		.btequ		5,u3c0		; Data output select bit
ckpol_u3	.btequ		6,u3c0		; Clk polarity select bit
uform_u3	.btequ		7,u3c0		; Transfer format select bit
;
;-------------------------------------------------------
;	UART3 Transmit/Receive Control Register 1
;-------------------------------------------------------
u3c1		.equ		032dh
;
te_u3		.btequ		0,u3c1		; Transmit enable bit
ti_u3		.btequ		1,u3c1		; Transmit buffer empty flag
re_u3		.btequ		2,u3c1		; Receive enable bit
ri_u3		.btequ		3,u3c1		; Receive complete flag
u3irs		.btequ		4,u3c1		; Transmit interrupt cause select bit
u3rrm		.btequ		5,u3c1		; Continuous receive mode enable bit
u3lch		.btequ		6,u3c1		; Data logic select bit
u3ere		.btequ		7,u3c1		; Clock divide synch stop bit/error signal output enable bit
;
;-------------------------------------------------------
;	UART3 Receive Buffer Register
;-------------------------------------------------------
u3rb		.equ		032eh
u3rbl		.equ		u3rb		; UART3 receive buffer low
u3rbh		.equ		u3rb+1		; UART3 receive buffer high
;
abt_u3		.btequ		3,u3rbh		; Arbitration lost detecting flag
oer_u3		.btequ		4,u3rbh		; Overrun error flag
fer_u3		.btequ		5,u3rbh		; Framing error flag
per_u3		.btequ		6,u3rbh		; Parity error flag
sum_u3		.btequ		7,u3rbh		; Error sum flag
;
;-------------------------------------------------------
;	UART2 Special Mode Register 4
;-------------------------------------------------------
u2smr4		.equ		0334h
;
stareq_u2	.btequ		0,u2smr4	; Start condition generate bit
rstareq_u2	.btequ		1,u2smr4	; Restart condition generate bit
stpreq_u2	.btequ		2,u2smr4	; Stop condition generate bit
stapsel_u2	.btequ		3,u2smr4	; SCL, SDA output select bit
ackd_u2		.btequ		4,u2smr4	; ACK data bit
ackc_u2		.btequ		5,u2smr4	; ACK data output enable bit
sclhi_u2	.btequ		6,u2smr4	; SCL output stop enable bit
swc9_u2		.btequ		7,u2smr4	; SCL wait output bit 3
;
;-------------------------------------------------------
;	UART2 Special Mode Register 3
;-------------------------------------------------------
u2smr3		.equ		0335h
;
sse_u2		.btequ		0,u2smr3	; /SS port function enable bit
ckph_u2		.btequ		1,u2smr3	; Clock phase set bit
dinc_u2		.btequ		2,u2smr3	; Serial input port set bit
nodc_u2		.btequ		3,u2smr3	; Clock output select bit
err_u2		.btequ		4,u2smr3	; Fault error flag
dl0_u2		.btequ		5,u2smr3	; SDA2 digital delay time set bit 0
dl1_u2		.btequ		6,u2smr3	; SDA2 digital delay time set bit 1
dl2_u2		.btequ		7,u2smr3	; SDA2 digital delay time set bit 2
;
;-------------------------------------------------------
;	UART2 Special Mode Register 2
;-------------------------------------------------------
u2smr2		.equ		0336h
;
iicm2_u2	.btequ		0,u2smr2	; IIC mode select bit 2
csc_u2		.btequ		1,u2smr2	; Clock synchronous bit
swc_u2		.btequ		2,u2smr2	; SCL wait output bit
als_u2		.btequ		3,u2smr2	; SDA output stop bit
stc_u2		.btequ		4,u2smr2	; UART2 initialize bit
swc2_u2		.btequ		5,u2smr2	; SCL wait output bit 2
sdhi_u2		.btequ		6,u2smr2	; SDA output inhibit bit
sclkdiv_u2	.btequ		7,u2smr2	; Clock divide set bit
;
;-------------------------------------------------------
;	UART2 Special Mode Register
;-------------------------------------------------------
u2smr		.equ		0337h
;
iicm_u2		.btequ		0,u2smr		; IIC mode select bit
abc_u2		.btequ		1,u2smr		; Arbitration lost detecting flag control bit
bbs_u2		.btequ		2,u2smr		; Bus busy flag
lsyn_u2		.btequ		3,u2smr		; SCLL sync output enable bit
abscs_u2	.btequ		4,u2smr		; Bus collision detect sampling clock select bit
acse_u2		.btequ		5,u2smr		; Auto-clear func select bit of tx enable bit
sss_u2		.btequ		6,u2smr		; Tx start condition select bit
su1him_u2	.btequ		7,u2smr		; clock divide synch enable bit
;
;-------------------------------------------------------
;	UART2 Transmit/Receive Mode Register
;-------------------------------------------------------
u2mr		.equ		0338h
;
smd0_u2		.btequ		0,u2mr		; Serial I/O mode select bit 0
smd1_u2		.btequ		1,u2mr		; Serial I/O mode select bit 1
smd2_u2		.btequ		2,u2mr		; Serial I/O mode select bit 2
ckdir_u2	.btequ		3,u2mr		; Internal/external clock select bit
stps_u2		.btequ		4,u2mr		; Stop bit length select bit
pry_u2		.btequ		5,u2mr		; Odd/even parity select bit
prye_u2		.btequ		6,u2mr		; Parity enable bit
iopol_u2	.btequ		7,u2mr		; Tx,Rx input/output polarity switch bit
;
;-------------------------------------------------------
;	UART2 Bit Rate Generator
;-------------------------------------------------------
u2brg		.equ		0339h
;
;-------------------------------------------------------
;	UART2 Transmit Buffer Register
;-------------------------------------------------------
u2tb		.equ		033ah
;
u2tbl		.equ		u2tb		; UART2 transmit buffer low
u2tbh		.equ		u2tb+1		; UART2 transmit buffer high
;
;-------------------------------------------------------
;	UART2 Transmit/Receive Control Register 0
;-------------------------------------------------------
u2c0		.equ		033ch
;
clk0_u2		.btequ		0,u2c0		; Brg count source select bit 0
clk1_u2		.btequ		1,u2c0		; Brg count source select bit 1
crs_u2		.btequ		2,u2c0		; Cts/rts function select bit
txept_u2	.btequ		3,u2c0		; Transmit register empty flag
crd_u2		.btequ		4,u2c0		; Cts/rts disable bit
nch_u2		.btequ		5,u2c0		; Data output select bit
ckpol_u2	.btequ		6,u2c0		; Clk polarity select bit
uform_u2	.btequ		7,u2c0		; Transfer format select bit
;
;-------------------------------------------------------
;	UART2 Transmit/Receive Control Register 1
;-------------------------------------------------------
u2c1		.equ		033dh
;
te_u2		.btequ		0,u2c1		; Transmit enable bit
ti_u2		.btequ		1,u2c1		; Transmit buffer empty flag
re_u2		.btequ		2,u2c1		; Receive enable bit
ri_u2		.btequ		3,u2c1		; Receive complete flag
u2irs		.btequ		4,u2c1		; Transmit interrupt cause select bit
u2rrm		.btequ		5,u2c1		; Continuous receive mode enable bit
u2lch		.btequ		6,u2c1		; Data logic select bit
u2ere		.btequ		7,u2c1		; Clock divide synch stop bit/error signal output enable bit
;
;---