sfr_245.inc

Mitsubishi M30245 SampleCode

intst1		.btequ		1,usbis		; EP1 OUT interrupt status flag
intst2		.btequ		2,usbis		; EP2 IN interrupt status flag
intst3		.btequ		3,usbis		; EP2 OUT interrupt status flag
intst4		.btequ		4,usbis		; EP3 IN interrupt status flag
intst5		.btequ		5,usbis		; EP3 OUT interrupt status flag
intst6		.btequ		6,usbis		; EP4 IN interrupt status flag
intst7		.btequ		7,usbis		; EP4 OUT interrupt status flag
intst8		.btequ		0,usbish	; Error interrupt status flag
;
;-------------------------------------------------------
;	USB Interrupt Clear Register
;-------------------------------------------------------
usbic		.equ		0286h
usbicl		.equ		usbic		; low byte
usbich		.equ		usbic+1		; high byte
;
intcl0		.btequ		0,usbic		; Clear EP1 IN interrupt status flag
intcl1		.btequ		1,usbic		; Clear EP1 OUT interrupt status flag
intcl2		.btequ		2,usbic		; Clear EP2 IN interrupt status flag
intcl3		.btequ		3,usbic		; Clear EP2 OUT interrupt status flag
intcl4		.btequ		4,usbic		; Clear EP3 IN interrupt status flag
intcl5		.btequ		5,usbic		; Clear EP3 OUT interrupt status flag
intcl6		.btequ		6,usbic		; Clear EP4 IN interrupt status flag
intcl7		.btequ		7,usbic		; Clear EP4 OUT interrupt status flag
intcl8		.btequ		0,usbich	; Clear Error interrupt status flag
;
;-------------------------------------------------------
;	USB Interrupt Enable Register
;-------------------------------------------------------
usbie		.equ		0288h
usbiel		.equ		usbie		; low byte
usbieh		.equ		usbie+1		; high byte
;
inten0		.btequ		0,usbie		; EP1 IN interrupt enable bit
inten1		.btequ		1,usbie		; EP1 OUT interrupt enable bit
inten2		.btequ		2,usbie		; EP2 IN interrupt enable bit
inten3		.btequ		3,usbie		; EP2 OUT interrupt enable bit
inten4		.btequ		4,usbie		; EP3 IN interrupt enable bit
inten5		.btequ		5,usbie		; EP3 OUT interrupt enable bit
inten6		.btequ		6,usbie		; EP4 IN interrupt enable bit
inten7		.btequ		7,usbie		; EP4 OUT interrupt enable bit
inten8		.btequ		0,usbieh	; Error interrupt enable bit
;
;-------------------------------------------------------
;	USB Frame Number Register
;-------------------------------------------------------
usbfn		.equ		028ah
usbfnl		.equ		usbfn		; low byte
usbfnh		.equ		usbfn+1		; high byte
;
;-------------------------------------------------------
;	USB ISO Control Register
;-------------------------------------------------------
usbisoc		.equ		028ch
;
auto_fl		.btequ		0,usbisoc	; Auto flush enable bit
iso_upd		.btequ		1,usbisoc	; ISO update enable bit
art_sof_ena	.btequ		2,usbisoc	; Artificial SOF enable bit
art_sof_set	.btequ		3,usbisoc	; Set Artificial SOF flag
clr_art_sof	.btequ		4,usbisoc	; Clear artificial SOF flag
;
;-------------------------------------------------------
;	USB Endpoint Enable Register
;-------------------------------------------------------
usbepen		.equ		028eh
;
ep1_out		.btequ		0,usbepen	; EP1 OUT enable bit
ep1_in		.btequ		1,usbepen	; EP1 IN enable bit
ep2_out		.btequ		2,usbepen	; EP2 OUT enable bit
ep2_in		.btequ		3,usbepen	; EP2 IN enable bit
ep3_out		.btequ		4,usbepen	; EP3 OUT enable bit
ep3_in		.btequ		5,usbepen	; EP3 IN enable bit
ep4_out		.btequ		6,usbepen	; EP4 OUT enable bit
ep4_in		.btequ		7,usbepen	; EP4 IN enable bit
;
;-------------------------------------------------------
;	USB DMA0 Request Register
;-------------------------------------------------------
usbdma0		.equ		0290h
usbdma0l	.equ		usbdma0		; low byte
usbdma0h	.equ		usbdma0+1	; high byte
;
dma0r0		.btequ		0,usbdma0	; EP0 IN FIFO write request bit
dma0r1		.btequ		1,usbdma0	; EP1 IN FIFO write request bit
dma0r2		.btequ		2,usbdma0	; EP2 IN FIFO write request bit
dma0r3		.btequ		3,usbdma0	; EP3 IN FIFO write request bit
dma0r4		.btequ		4,usbdma0	; EP4 IN FIFO write request bit
dma0r5		.btequ		5,usbdma0	; EP0 OUT FIFO read request bit
dma0r6		.btequ		6,usbdma0	; EP1 OUT FIFO read request bit
dma0r7		.btequ		7,usbdma0	; EP2 OUT FIFO read request bit
dma0r8		.btequ		0,usbdma0h	; EP3 OUT FIFO read request bit
dma0r9		.btequ		1,usbdma0h	; EP4 OUT FIFO read request bit
;
;-------------------------------------------------------
;	USB DMA1 Request Register
;-------------------------------------------------------
usbdma1		.equ		0292h
usbdma1l	.equ		usbdma1		; low byte
usbdma1h	.equ		usbdma1+1	; high byte
;
dma1r0		.btequ		0,usbdma1	; EP0 IN FIFO write request bit
dma1r1		.btequ		1,usbdma1	; EP1 IN FIFO write request bit
dma1r2		.btequ		2,usbdma1	; EP2 IN FIFO write request bit
dma1r3		.btequ		3,usbdma1	; EP3 IN FIFO write request bit
dma1r4		.btequ		4,usbdma1	; EP4 IN FIFO write request bit
dma1r5		.btequ		5,usbdma1	; EP0 OUT FIFO read request bit
dma1r6		.btequ		6,usbdma1	; EP1 OUT FIFO read request bit
dma1r7		.btequ		7,usbdma1	; EP2 OUT FIFO read request bit
dma1r8		.btequ		0,usbdma1h	; EP3 OUT FIFO read request bit
dma1r9		.btequ		1,usbdma1h	; EP4 OUT FIFO read request bit
;
;-------------------------------------------------------
;	USB DMA2 Request Register
;-------------------------------------------------------
usbdma2		.equ		0294h
usbdma2l	.equ		usbdma2		; low byte
usbdma2h	.equ		usbdma2+1	; high byte
;
dma2r0		.btequ		0,usbdma2	; EP0 IN FIFO write request bit
dma2r1		.btequ		1,usbdma2	; EP1 IN FIFO write request bit
dma2r2		.btequ		2,usbdma2	; EP2 IN FIFO write request bit
dma2r3		.btequ		3,usbdma2	; EP3 IN FIFO write request bit
dma2r4		.btequ		4,usbdma2	; EP4 IN FIFO write request bit
dma2r5		.btequ		5,usbdma2	; EP0 OUT FIFO read request bit
dma2r6		.btequ		6,usbdma2	; EP1 OUT FIFO read request bit
dma2r7		.btequ		7,usbdma2	; EP2 OUT FIFO read request bit
dma2r8		.btequ		0,usbdma2h	; EP3 OUT FIFO read request bit
dma2r9		.btequ		1,usbdma2h	; EP4 OUT FIFO read request bit
;
;-------------------------------------------------------
;	USB DMA3 Request Register
;-------------------------------------------------------
usbdma3		.equ		0296h
usbdma3l	.equ		usbdma3		; low byte
usbdma3h	.equ		usbdma3+1	; high byte
;
dma3r0		.btequ		0,usbdma3	; EP0 IN FIFO write request bit
dma3r1		.btequ		1,usbdma3	; EP1 IN FIFO write request bit
dma3r2		.btequ		2,usbdma3	; EP2 IN FIFO write request bit
dma3r3		.btequ		3,usbdma3	; EP3 IN FIFO write request bit
dma3r4		.btequ		4,usbdma3	; EP4 IN FIFO write request bit
dma3r5		.btequ		5,usbdma3	; EP0 OUT FIFO read request bit
dma3r6		.btequ		6,usbdma3	; EP1 OUT FIFO read request bit
dma3r7		.btequ		7,usbdma3	; EP2 OUT FIFO read request bit
dma3r8		.btequ		0,usbdma3h	; EP3 OUT FIFO read request bit
dma3r9		.btequ		1,usbdma3h	; EP4 OUT FIFO read request bit
;
;-------------------------------------------------------
;	USB Endpoint 0 Control/Status Register
;-------------------------------------------------------
ep0cs		.equ		0298h
ep0csl		.equ		ep0cs		; low byte
ep0csh		.equ		ep0cs+1		; high byte
;
ep0csr0		.btequ		0,ep0cs		; OUT_BUF_RDY flag
ep0csr1		.btequ		1,ep0cs		; IN_BUF_RDY flag
ep0csr2		.btequ		2,ep0cs		; SETUP flag
ep0csr3		.btequ		3,ep0cs		; DATA_END flag
ep0csr4		.btequ		4,ep0cs		; FORCE_STALL flag
ep0csr5		.btequ		5,ep0cs		; SETUP_END flag
ep0csr6		.btequ		6,ep0cs		; CLR_OUT_BUF_RDY
ep0csr7		.btequ		7,ep0cs		; SET_IN_BUF_RDY
ep0csr8		.btequ		0,ep0csh	; CLR_SETUP
ep0csr9		.btequ		1,ep0csh	; SET_DATA_END
ep0csr10	.btequ		2,ep0csh	; CLR_FORCE_STALL
ep0csr11	.btequ		3,ep0csh	; CLR_SETUP_END
ep0csr12	.btequ		4,ep0csh	; SEND_STALL
ep0csr13	.btequ		5,ep0csh	; DATA_END_MASK
;
;-------------------------------------------------------
;	USB Endpoint 0 Max Packet Register
;-------------------------------------------------------
ep0mp		.equ		029ah
ep0mpl		.equ		ep0mp		; low byte
ep0mph		.equ		ep0mp+1		; high byte
;
wrt_cont	.btequ		7,ep0mp		; Control write continuous transfer mode
rd_cont		.btequ		0,ep0mph	; Control read continuous transfer mode
;
;-------------------------------------------------------
;	USB Endpoint 0 Write Count Register
;-------------------------------------------------------
ep0wc		.equ		029ch
ep0wcl		.equ		ep0wc		; low byte
ep0wch		.equ		ep0wc+1		; high byte
;
;-------------------------------------------------------
;	USB Endpoint 1 IN Control/Status Register
;-------------------------------------------------------
ep1ics		.equ		029eh
ep1icsl		.equ		ep1ics		; low byte
ep1icsh		.equ		ep1ics+1	; high byte
;
in1csr0		.btequ		0,ep1ics	; IN_BUF_STS0 flag
in1csr1		.btequ		1,ep1ics	; IN_BUF_STS1 flag
in1csr2		.btequ		2,ep1ics	; UNDER-RUN flag
in1csr3		.btequ		3,ep1ics	; SET_IN_BUF_RDY
in1csr4		.btequ		4,ep1ics	; CLR_UNDER_RUN
in1csr5		.btequ		5,ep1ics	; TOGGLE_INT
in1csr6		.btequ		6,ep1ics	; FLUSH
in1csr7		.btequ		7,ep1ics	; INTPT
in1csr8		.btequ		0,ep1icsh	; ISO
in1csr9		.btequ		1,ep1icsh	; SEND_STALL
in1csr10	.btequ		2,ep1icsh	; AUTO_SET
;
;-------------------------------------------------------
;	USB Endpoint 1 IN Max Packet Register
;-------------------------------------------------------
ep1imp		.equ		02a0h
ep1impl		.equ		ep1imp		; low byte
ep1imph		.equ		ep1imp+1	; high byte
;
;-------------------------------------------------------
;	USB Endpoint 1 IN FIFO Configuration Register
;-------------------------------------------------------
ep1ifc		.equ		02a2h
ep1ifcl		.equ		ep1ifc		; low byte
ep1ifch		.equ		ep1ifc+1	; high byte
;
ep1i_buf_num0	.btequ		0,ep1ifc	; FIFO buffer start number bit0
ep1i_buf_num1	.btequ		1,ep1ifc	; FIFO buffer start number bit1
ep1i_buf_num2	.btequ		2,ep1ifc	; FIFO buffer start number bit2
ep1i_buf_num3	.btequ		3,ep1ifc	; FIFO buffer start number bit3
ep1i_buf_num4	.btequ		4,ep1ifc	; FIFO buffer start number bit4
ep1i_buf_num5	.btequ		5,ep1ifc	; FIFO buffer start number bit5
ep1i_buf_siz0	.btequ		6,ep1ifc	; FIFO buffer size bit0
ep1i_buf_siz1	.btequ		7,ep1ifc	; FIFO buffer size bit1
ep1i_buf_siz2	.btequ		0,ep1ifch	; FIFO buffer size bit2
ep1i_buf_siz3	.btequ		1,ep1ifch	; FIFO buffer size bit3
ep1i_dbl_buf	.btequ		2,ep1ifch	; Double buffer mode
ep1i_continue	.btequ		3,ep1ifch	; Continuous transfer mode
;
;-------------------------------------------------------
;	USB Endpoint 2 IN Control/Status Register
;-------------------------------------------------------
ep2ics		.equ		02a4h
ep2icsl		.equ		ep2ics		; low byte
ep2icsh		.equ		ep2ics+1	; high byte
;
in2csr0		.btequ		0,ep2ics	; IN_BUF_STS0 flag
in2csr1		.btequ		1,ep2ics	; IN_BUF_STS1 flag
in2csr2		.btequ		2,ep2ics	; UNDER-RUN flag
in2csr3		.btequ		3,ep2ics	; SET_IN_BUF_RDY
in2csr4		.btequ		4,ep2ics	; CLR_UNDER_RUN
in2csr5		.btequ		5,ep2ics	; TOGGLE_INT
in2csr6		.btequ		6,ep2ics	; FLUSH
in2csr7		.btequ		7,ep2ics	; INTPT
in2csr8		.btequ		0,ep2icsh	; ISO
in2csr9		.btequ		1,ep2icsh	; SEND_STALL
in2csr10	.btequ		2,ep2icsh	; AUTO_SET
;
;-------------------------------------------------------
;	USB Endpoint 2 IN Max Packet Register
;-------------------------------------------------------
ep2imp		.equ		02a6h
ep2impl		.equ		ep2imp		; low byte
ep2imph		.equ		ep2imp+1	; high byte
;
;-------------------------------------------------------
;	USB Endpoint 2 IN FIFO Configuration Register
;-------------------------------------------------------
ep2ifc		.equ		02a8h
ep2ifcl		.equ		ep2ifc		; low byte
ep2ifch		.equ		ep2ifc+1	; high byte
;
ep2i_buf_num0	.btequ		0,ep2ifc	; FIFO buffer start number bit0
ep2i_buf_num1	.btequ		1,ep2ifc	; FIFO buffer start number bit1
ep2i_buf_num2	.btequ		2,ep2ifc	; FIFO buffer start number bit2
ep2i_buf_num3	.btequ		3,ep2ifc	; FIFO buffer start number bit3
ep2i_buf_num4	.btequ		4,ep2ifc	; FIFO buffer start number bit4
ep2i_buf_num5	.btequ		5,ep2ifc	; FIFO buffer start number bit5
ep2i_buf_siz0	.btequ		6,ep2ifc	; FIFO buffer size bit0
ep2i_buf_siz1	.btequ		7,ep2ifc	; FIFO buffer size bit1
ep2i_buf_siz2	.btequ		0,ep2ifch	; FIFO buffer size bit2
ep2i_buf_siz3	.btequ		1,ep2ifch	; FIFO buffer size bit3
ep2i_dbl_buf	.btequ		2,ep2ifch	; Double buffer mode
ep2i_continue	.btequ		3,ep2ifch	; Continuous transfer mode
;
;-------------------------------------------------------
;	USB Endpoint 3 IN Control/Status Register
;-------------------------------------------------------
ep3ics		.equ		02aah
ep3icsl		.equ		ep3ics		; low byte
ep3icsh		.equ		ep3ics+1	; high byte
;
in3csr0		.btequ		0,ep3ics	; IN_BUF_STS0 flag
in3csr1		.btequ		1,ep3ics	; IN_BUF_STS1 flag
in3csr2		.btequ		2,ep3ics	; UNDER-RUN flag
in3csr3		.btequ		3,ep3ics	; SET_IN_BUF_RDY
in3csr4		.btequ		4,ep3ics	; CLR_UNDER_RUN
in3csr5		.btequ		5,ep3ics	; TOGGLE_INT
in3csr6		.btequ		6,ep3ics	; FLUSH
in3csr7		.btequ		7,ep3ics	; INTPT
in3csr8		.btequ		0,ep3icsh	; ISO
in3csr9		.btequ		1,ep3icsh	; SEND_STALL
in3csr10	.btequ		2,ep3icsh	; AUTO_SET
;
;-------------------------------------------------------
;	USB Endpoint 3 IN Max Packet Register
;-------------------------------------------------------
ep3imp		.equ		02ach
ep3impl		.equ		ep3imp		; low byte
ep3imph		.equ		ep3imp+1	; high byte
;
;-------------------------------------------------------
;	USB Endpoint 3 IN FIFO Configuration Register
;-------------------------------------------------------
ep3ifc		.equ		02aeh
ep3ifcl		.equ		ep3ifc		; low byte
ep3ifch		.equ		ep3ifc+1	; high byte
;
ep3i_buf_num0	.btequ		0,ep3ifc	; FIFO buffer start number bit0
ep3i_buf_num1	.btequ		1,ep3ifc	; FIFO buffer start number bit1