sfr_245.inc

Mitsubishi M30245 SampleCode

;*****************************************************************************
;*
;*	File Name:	sfr_245.inc
;*
;*	Content:	SFR Map for the M30245
;*
;*	Version:	1.00
;*	Released:	Mar. 5, 2002
;*
;*	NOTE: The byte labels for the registers correspond to acronyms
;*	 listed in the SFR MAP section of the M30245 Group spec
;*	NOTE: The bit labels for the registers correspond to the acronyms
;*	 listed in the register definitions
;*
;*	Copyright 2002 Mitsubishi Electric & Electronics USA
;*	All rights reserved
;*
;=============================================================================
;	$Log:$
;=============================================================================
;
;*****************************************************************************
;
;-------------------------------------------------------
;	Processor Mode Register 0
;-------------------------------------------------------
pm0		.equ		0004h
;
pm00		.btequ		0,pm0		; Processor mode bit0
pm01		.btequ		1,pm0		; Processor mode bit1
pm02		.btequ		2,pm0		; R/W mode select bit
pm03		.btequ		3,pm0		; Software reset bit
pm06		.btequ		6,pm0		; Port P4_0 to P4_3 function select bit
pm07		.btequ		7,pm0		; BCLK output disable bit
;
;-------------------------------------------------------
;	Processor Mode Register 1
;-------------------------------------------------------
pm1		.equ		0005h
;
pm16		.btequ		6,pm1		; WR length control bit
pm17		.btequ		7,pm1		; Wait bit
;
;-------------------------------------------------------
;	System Clock Control Register 0
;-------------------------------------------------------
cm0		.equ		0006h
;
cm02		.btequ		2,cm0		; Wait peripheral function clock stop bit
cm03		.btequ		3,cm0		; Xcin-Xcout drive capacity select bit
cm04		.btequ		4,cm0		; Port Xc select bit
cm05		.btequ		5,cm0		; Main clock stop bit
cm06		.btequ		6,cm0		; Main clock division select bit 0
cm07		.btequ		7,cm0		; System clock select bit
;
;-------------------------------------------------------
;	System Clock Control Register 1
;-------------------------------------------------------
cm1		.equ		0007h
;
cm10		.btequ		0,cm1		; All clock stop control bit
cm15		.btequ		5,cm1		; Xin-Xout drive capacity select bit
cm16		.btequ		6,cm1		; Main clock division select bit 1a
cm17		.btequ		7,cm1		; Main clock division select bit 1b
;
;-------------------------------------------------------
;	Chip Select Control Register
;-------------------------------------------------------
csr		.equ		0008h
;
cs0		.btequ		0,csr		; CS0 output enable bit
cs1		.btequ		1,csr		; CS1 output enable bit
cs2		.btequ		2,csr		; CS2 output enable bit
cs3		.btequ		3,csr		; CS3 output enable bit
cs0w		.btequ		4,csr		; CS0 wait bit
cs1w		.btequ		5,csr		; CS1 wait bit
cs2w		.btequ		6,csr		; CS2 wait bit
cs3w		.btequ		7,csr		; CS3 wait bit
;
;-------------------------------------------------------
;	Address Match Interrupt Enable Register
;-------------------------------------------------------
aier		.equ		0009h
;
aier0		.btequ		0,aier		; Address match interrupt 0 enable
aier1		.btequ		1,aier		; Address match interrupt 1 enable
;
;-------------------------------------------------------
;	Protect Register
;-------------------------------------------------------
prcr		.equ		000ah
;
prc0		.btequ		0,prcr		; Enable writting to system clock control register
prc1		.btequ		1,prcr		; Enable writting to processor mode register
prc2		.btequ		2,prcr		; Enable writting to port 9 direction register
;
;-------------------------------------------------------
;	USB Control Register
;-------------------------------------------------------
usbc		.equ		000ch
;
usbc5		.btequ		5,usbc		; USB clock enable bit
usbc6		.btequ		6,usbc		; USB SOF port select bit
usbc7		.btequ		7,usbc		; USB enable bit
;
;-------------------------------------------------------
;	Watchdog Timer Registers
;-------------------------------------------------------
wdts		.equ		000eh		; Watchdog timer start register
;
wdc		.equ		000fh		; Watchdog timer control register
wdc7		.btequ		7,wdc		; Divide by selection bit
;
;-------------------------------------------------------
;	Address Match Interrupt Register 0
;-------------------------------------------------------
rmad0		.equ		0010h
rmad0l		.equ		rmad0		; Address match interrupt register 0 low
rmad0m		.equ		rmad0+1		; Address match interrupt register 0 middle
rmad0h		.equ		rmad0+2		; Address match interrupt register 0 high
;
;-------------------------------------------------------
;	Address Match Interrupt Register 1
;-------------------------------------------------------
rmad1		.equ		0014h
rmad1l		.equ		rmad1		; Address match interrupt register 1 low
rmad1m		.equ		rmad1+1		; Address match interrupt register 1 middle
rmad1h		.equ		rmad1+2		; Address match interrupt register 1 high
;
;-------------------------------------------------------
;	Chip Select Expansion Register
;-------------------------------------------------------
cse		.equ		001bh
;
cse0w0		.btequ		0,cse		; CS0 wait expansion bit 0
cse0w1		.btequ		1,cse		; CS0 wait expansion bit 1
cse1w0		.btequ		2,cse		; CS1 wait expansion bit 0
cse1w1		.btequ		3,cse		; CS1 wait expansion bit 1
cse2w0		.btequ		4,cse		; CS2 wait expansion bit 0
cse2w1		.btequ		5,cse		; CS2 wait expansion bit 1
cse3w0		.btequ		6,cse		; CS3 wait expansion bit 0
cse3w1		.btequ		7,cse		; CS3 wait expansion bit 1
;
;-------------------------------------------------------
;	USB Attach/Detach Register
;-------------------------------------------------------
usbad		.equ		001fh
;
p90_2nd		.btequ		0,usbad		; Port 90-Second mode
attach		.btequ		1,usbad		; Attach / detach select bit
vbdt		.btequ		7,usbad		; Vbus detect enable bit
;
;-------------------------------------------------------
;	DMA0 Source Pointer Register
;-------------------------------------------------------
sar0		.equ		0020h
sar0l		.equ		sar0		; DMA0 source address low byte
sar0m		.equ		sar0+1		; DMA0 source address middle byte
sar0h		.equ		sar0+2		; DMA0 source address high byte
;
;-------------------------------------------------------
;	DMA0 Destination Pointer Register
;-------------------------------------------------------
dar0		.equ		0024h
dar0l		.equ		dar0		; DMA0 destination address low byte
dar0m		.equ		dar0+1		; DMA0 destination address middle byte
dar0h		.equ		dar0+2		; DMA0 destination address high byte
;
;-------------------------------------------------------
;	DMA0 Transfer Counter Register
;-------------------------------------------------------
tcr0		.equ		0028h
tcr0l		.equ		tcr0		; DMA0 transfer counter low
tcr0h		.equ		tcr0+1		; DMA0 transfer counter high
;
;-------------------------------------------------------
;	DMA0 Control Register
;-------------------------------------------------------
dm0con		.equ		002ch
;
dmbit_d0	.btequ		0,dm0con	; Transfer unit bit select bit
dmasl_d0	.btequ		1,dm0con	; Repeat transfer mode select bit
dmas_d0		.btequ		2,dm0con	; DMA0 request bit
dmae_d0		.btequ		3,dm0con	; DMA0 enable bit
dsd_d0		.btequ		4,dm0con	; Source address direction select bit
dad_d0		.btequ		5,dm0con	; Destination address direction select bit
;
;-------------------------------------------------------
;	DMA1 Source Pointer Register
;-------------------------------------------------------
sar1		.equ		0030h
sar1l		.equ		sar1		; DMA1 source address low byte
sar1m		.equ		sar1+1		; DMA1 source address middle byte
sar1h		.equ		sar1+2		; DMA1 source address high byte
;
;-------------------------------------------------------
;	DMA1 Destination Pointer Register
;-------------------------------------------------------
dar1		.equ		0034h
dar1l		.equ		dar1		; DMA1 destination address low byte
dar1m		.equ		dar1+1		; DMA1 destination address middle byte
dar1h		.equ		dar1+2		; DMA1 destination address high byte
;
;-------------------------------------------------------
;	DMA1 Transfer Counter Register
;-------------------------------------------------------
tcr1		.equ		0038h
tcr1l		.equ		tcr1		; DMA1 transfer counter low
tcr1h		.equ		tcr1+1		; DMA1 transfer counter high
;
;-------------------------------------------------------
;	DMA1 Control Register
;-------------------------------------------------------
dm1con		.equ		003ch
;
dmbit_d1	.btequ		0,dm1con	; Transfer unit bit select bit
dmasl_d1	.btequ		1,dm1con	; Repeat transfer mode select bit
dmas_d1		.btequ		2,dm1con	; DMA1 request bit
dmae_d1		.btequ		3,dm1con	; DMA1 enable bit
dsd_d1		.btequ		4,dm1con	; Source address direction select bit
dad_d1		.btequ		5,dm1con	; Destination address direction select bit
;
;-------------------------------------------------------
;	Key Input Interrupt Register
;-------------------------------------------------------
kupic		.equ		0041h
;
ilvl0_kupic	.btequ		0,kupic		; Interrupt priority level select bit0
ilvl1_kupic	.btequ		1,kupic		; Interrupt priority level select bit1
ilvl2_kupic	.btequ		2,kupic		; Interrupt priority level select bit2
ir_kupic	.btequ		3,kupic		; Interrupt request bit
;
;-------------------------------------------------------
;	UART2 Receive Interrupt	Control Register
;-------------------------------------------------------
s2ric		.equ		0042h
;
ilvl0_s2ric	.btequ		0,s2ric		; Interrupt priority level select bit0
ilvl1_s2ric	.btequ		1,s2ric		; Interrupt priority level select bit1
ilvl2_s2ric	.btequ		2,s2ric		; Interrupt priority level select bit2
ir_s2ric	.btequ		3,s2ric		; Interrupt request bit
;
;-------------------------------------------------------
;	UART1/3 Bus Collision Interrupt Control Register
;-------------------------------------------------------
s13bcnic	.equ		0043h
;
ilvl0_s13bcnic	.btequ		0,s13bcnic	; Interrupt priority level select bit0
ilvl1_s13bcnic	.btequ		1,s13bcnic	; Interrupt priority level select bit1
ilvl2_s13bcnic	.btequ		2,s13bcnic	; Interrupt priority level select bit2
ir_s13bcnic	.btequ		3,s13bcnic	; Interrupt request bit
;
;-------------------------------------------------------
;	INT1 Interrupt Control Register
;-------------------------------------------------------
int1ic		.equ		0044h
;
ilvl0_int1ic	.btequ		0,int1ic	; Interrupt priority level select bit0
ilvl1_int1ic	.btequ		1,int1ic	; Interrupt priority level select bit1
ilvl2_int1ic	.btequ		2,int1ic	; Interrupt priority level select bit2
ir_int1ic	.btequ		3,int1ic	; Interrupt request bit
pol_int1ic	.btequ		4,int1ic	; Interrupt polarity select bit
;
;-------------------------------------------------------
;	Timer A1 Interrupt Control Register
;-------------------------------------------------------
ta1ic		.equ		0045h
;
ilvl0_ta1ic	.btequ		0,ta1ic		; Interrupt priority level select bit0
ilvl1_ta1ic	.btequ		1,ta1ic		; Interrupt priority level select bit1
ilvl2_ta1ic	.btequ		2,ta1ic		; Interrupt priority level select bit2
ir_ta1ic	.btequ		3,ta1ic		; Interrupt request bit
;
;-------------------------------------------------------
;	USB Endpoint 0 Interrupt Control Register
;-------------------------------------------------------
ep0ic		.equ		0046h
;
ilvl0_ep0ic	.btequ		0,ep0ic		; Interrupt priority level select bit0
ilvl1_ep0ic	.btequ		1,ep0ic		; Interrupt priority level select bit1
ilvl2_ep0ic	.btequ		2,ep0ic		; Interrupt priority level select bit2
ir_ep0ic	.btequ		3,ep0ic		; Interrupt request bit
;
;-------------------------------------------------------
;	Timer A2 Interrupt Control Register
;-------------------------------------------------------
ta2ic		.equ		0047h
;
ilvl0_ta2ic	.btequ		0,ta2ic		; Interrupt priority level select bit0
ilvl1_ta2ic	.btequ		1,ta2ic		; Interrupt priority level select bit1
ilvl2_ta2ic	.btequ		2,ta2ic		; Interrupt priority level select bit2
ir_ta2ic	.btequ		3,ta2ic		; Interrupt request bit
;
;-------------------------------------------------------
;	UART1/SSI1 Receive Interrupt
;-------------------------------------------------------
s1ric		.equ		0048h
;
ilvl0_s1ric	.btequ		0,s1ric		; Interrupt priority level select bit0
ilvl1_s1ric	.btequ		1,s1ric		; Interrupt priority level select bit1
ilvl2_s1ric	.btequ		2,s1ric		; Interrupt priority level select bit2
ir_s1ric	.btequ		3,s1ric		; Interrupt request bit
;
;-------------------------------------------------------
;	UART0/2 Bus Collision Interrupt Control Register
;-------------------------------------------------------
s02bcnic	.equ		0049h
;
ilvl0_s02bcnic	.btequ		0,s02bcnic	; Interrupt priority level select bit0
ilvl1_s02bcnic	.btequ		1,s02bcnic	; Interrupt priority level select bit1
ilvl2_s02bcnic	.btequ		2,s02bcnic	; Interrupt priority level select bit2
ir_s02bcnic	.btequ		3,s02bcnic	; Interrupt request bit
;