sfr245.h

Mitsubishi M30245 SampleCode

------------------------------------------------------*/
union word_def usbie_addr;
#define		usbie	usbie_addr.word
#define		usbiel	usbie_addr.byte.low		/* low byte */
#define		usbieh	usbie_addr.byte.high	/* high byte */

#define		inten0	usbie_addr.bit.b0	/* Endpoint 1 IN int enable flag */
#define		inten1	usbie_addr.bit.b1	/* Endpoint 1 OUT int enable flag */
#define		inten2	usbie_addr.bit.b2	/* Endpoint 2 IN int enable flag */
#define		inten3	usbie_addr.bit.b3	/* Endpoint 2 OUT int enable flag */
#define		inten4	usbie_addr.bit.b4	/* Endpoint 3 IN int enable flag */
#define		inten5	usbie_addr.bit.b5	/* Endpoint 3 OUT int enable flag */
#define		inten6	usbie_addr.bit.b6	/* Endpoint 4 IN int enable flag */
#define		inten7	usbie_addr.bit.b7	/* Endpoint 4 OUT int enable flag */
#define		inten8	usbie_addr.bit.b8	/* Error interrupt enable flag */

/*------------------------------------------------------
	USB frame number register
------------------------------------------------------*/
union word_def usbfn_addr;
#define		usbfn		usbfn_addr.word
#define		usbfnl		usbfnl_addr.byte	/* low byte */
#define		usbfnh		usbfnh_addr.byte	/* high byte */

/*------------------------------------------------------
	USB ISO control register
------------------------------------------------------*/
union word_def usbisoc_addr;
#define		usbisoc		usbisoc_addr.word
#define		usbisocl	usbisoc_addr.byte.low	/* low byte */

#define		auto_fl		usbisoc_addr.bit.b0	/* Auto Flush bit */
#define		iso_upd		usbisoc_addr.bit.b1	/* ISO update bit */
#define		art_sof_ena	usbisoc_addr.bit.b2	/* Artificial SOF bit */
#define		art_sof_set	usbisoc_addr.bit.b3	/* Set artificial SOF flag */
#define		clr_art_sof	usbisoc_addr.bit.b4	/* Clear artificial SOF flag */

/*------------------------------------------------------
	USB Endpoint enable register
------------------------------------------------------*/
union word_def usbepen_addr;
#define		usbepen		usbepen_addr.word
#define		usbepenl	usbepen_addr.byte.low	/* low byte */

#define		ep1_out	usbepen_addr.bit.b0	/* Endpoint 1 OUT enable bit */
#define		ep1_in	usbepen_addr.bit.b1	/* Endpoint 1 IN enable bit */
#define		ep2_out	usbepen_addr.bit.b2	/* Endpoint 2 OUT enable bit */
#define		ep2_in	usbepen_addr.bit.b3	/* Endpoint 2 IN enable bit */
#define		ep3_out	usbepen_addr.bit.b4	/* Endpoint 3 OUT enable bit */
#define		ep3_in	usbepen_addr.bit.b5	/* Endpoint 3 IN enable bit */
#define		ep4_out	usbepen_addr.bit.b6	/* Endpoint 4 OUT enable bit */
#define		ep4_in	usbepen_addr.bit.b7	/* Endpoint 4 IN enable bit */

/*------------------------------------------------------
	USB DMA0 request register
------------------------------------------------------*/
union word_def usbdma0_addr;
#define		usbdma0	usbdma0_addr.word
#define		usbdma0l 	usbdma0_addr.byte.low  	/* low byte */
#define		usbdma0h 	usbdma0_addr.byte.high	/* high byte */

#define		dma0r0	usbdma0_addr.bit.b0	/* EP0 IN FIFO write req sel bit */
#define		dma0r1	usbdma0_addr.bit.b1	/* EP1 IN FIFO write req sel bit */
#define		dma0r2	usbdma0_addr.bit.b2	/* EP2 IN FIFO write req sel bit */
#define		dma0r3	usbdma0_addr.bit.b3	/* EP3 IN FIFO write req sel bit */
#define		dma0r4	usbdma0_addr.bit.b4	/* EP4 IN FIFO write req sel bit */
#define		dma0r5 	usbdma0_addr.bit.b5	/* EP0 OUT FIFO read req sel bit */	
#define		dma0r6	usbdma0_addr.bit.b6	/* EP1 OUT FIFO read req sel bit */
#define		dma0r7 	usbdma0_addr.bit.b7	/* EP2 OUT FIFO read req sel bit */
#define		dma0r8 	usbdma0_addr.bit.b8	/* EP3 OUT FIFO read req sel bit */
#define		dma0r9 	usbdma0_addr.bit.b9	/* EP4 OUT FIFO read req sel bit */

/*------------------------------------------------------
	USB DMA1 request register
------------------------------------------------------*/
union word_def usbdma1_addr;
#define		usbdma1	usbdma1_addr.word
#define		usbdma1l 	usbdma1_addr.byte.low  	/* low byte */
#define		usbdma1h 	usbdma1_addr.byte.high	/* high byte */

#define		dma1r0 	usbdma1_addr.bit.b0	/* EP1 IN FIFO write req sel bit */
#define		dma1r1	usbdma1_addr.bit.b1	/* EP2 IN FIFO write req sel bit */
#define		dma1r2	usbdma1_addr.bit.b2	/* EP3 IN FIFO write req sel bit */
#define		dma1r3	usbdma1_addr.bit.b3	/* EP4 IN FIFO write req sel bit */
#define		dma1r4	usbdma1_addr.bit.b4	/* EP1 OUT FIFO read req sel bit */
#define		dma1r5 	usbdma1_addr.bit.b5	/* EP2 OUT FIFO read req sel bit */
#define		dma1r6	usbdma1_addr.bit.b6	/* EP3 OUT FIFO read req sel bit */
#define		dma1r7 	usbdma1_addr.bit.b7	/* EP4 OUT FIFO read req sel bit */
#define		dma1r8 	usbdma1_addr.bit.b8	/* EP3 OUT FIFO read req sel bit */
#define		dma1r9 	usbdma1_addr.bit.b9	/* EP4 OUT FIFO read req sel bit */

/*------------------------------------------------------
	USB DMA2 request register
------------------------------------------------------*/
union word_def usbdma2_addr;
#define		usbdma2	usbdma2_addr.word
#define		usbdma2l 	usbdma2_addr.byte.low  	/* low byte */
#define		usbdma2h 	usbdma2_addr.byte.high	/* high byte */

#define		dma2r0 	usbdma2_addr.bit.b0	/* EP1 IN FIFO write req sel bit */
#define		dma2r1	usbdma2_addr.bit.b1	/* EP2 IN FIFO write req sel bit */
#define		dma2r2	usbdma2_addr.bit.b2	/* EP3 IN FIFO write req sel bit */
#define		dma2r3	usbdma2_addr.bit.b3	/* EP4 IN FIFO write req sel bit */
#define		dma2r4	usbdma2_addr.bit.b4	/* EP1 OUT FIFO read req sel bit */
#define		dma2r5 	usbdma2_addr.bit.b5	/* EP2 OUT FIFO read req sel bit */
#define		dma2r6	usbdma2_addr.bit.b6	/* EP3 OUT FIFO read req sel bit */
#define		dma2r7 	usbdma2_addr.bit.b7	/* EP4 OUT FIFO read req sel bit */
#define		dma2r8 	usbdma2_addr.bit.b8	/* EP3 OUT FIFO read req sel bit */
#define		dma2r9 	usbdma2_addr.bit.b9	/* EP4 OUT FIFO read req sel bit */

/*------------------------------------------------------
	USB DMA3 request register
------------------------------------------------------*/
union word_def usbdma3_addr;
#define		usbdma3	usbdma3_addr.word
#define		usbdma3l 	usbdma3_addr.byte.low  	/* low byte */
#define		usbdma3h 	usbdma3_addr.byte.high	/* high byte */

#define		dma3r0 	usbdma3_addr.bit.b0	/* EP1 IN FIFO write req sel bit */
#define		dma3r1	usbdma3_addr.bit.b1	/* EP2 IN FIFO write req sel bit */
#define		dma3r2	usbdma3_addr.bit.b2	/* EP3 IN FIFO write req sel bit */
#define		dma3r3	usbdma3_addr.bit.b3	/* EP4 IN FIFO write req sel bit */
#define		dma3r4	usbdma3_addr.bit.b4	/* EP1 OUT FIFO read req sel bit */
#define		dma3r5 	usbdma3_addr.bit.b5	/* EP2 OUT FIFO read req sel bit */
#define		dma3r6	usbdma3_addr.bit.b6	/* EP3 OUT FIFO read req sel bit */
#define		dma3r7 	usbdma3_addr.bit.b7	/* EP4 OUT FIFO read req sel bit */
#define		dma3r8 	usbdma3_addr.bit.b8	/* EP3 OUT FIFO read req sel bit */
#define		dma3r9 	usbdma3_addr.bit.b9	/* EP4 OUT FIFO read req sel bit */

/*------------------------------------------------------
	USB EP0 control/status register
------------------------------------------------------*/
union word_def ep0cs_addr;
#define		ep0cs		ep0cs_addr.word
#define		ep0csl		ep0cs_addr.byte.low		/* low byte */
#define		ep0csh		ep0cs_addr.byte.high	/* high byte */

#define		ep0csr0		ep0cs_addr.bit.b0 	/* OUT_BUF_RDY flag */
#define		ep0csr1		ep0cs_addr.bit.b1 	/* IN_BUF_RDY flag */
#define		ep0csr2		ep0cs_addr.bit.b2 	/* SETUP flag */
#define		ep0csr3		ep0cs_addr.bit.b3 	/* DATA_END flag */
#define		ep0csr4		ep0cs_addr.bit.b4 	/* FORCE_STALL flag */
#define		ep0csr5		ep0cs_addr.bit.b5 	/* SETUP_END flag */
#define		ep0csr6		ep0cs_addr.bit.b6 	/* CLEAR_OUT_BUF_RDY */
#define		ep0csr7		ep0cs_addr.bit.b7 	/* SET_IN_BUF_RDY */
#define		ep0csr8		ep0cs_addr.bit.b8 	/* CLR_SETUP */
#define		ep0csr9		ep0cs_addr.bit.b9 	/* SET_DATA_END */
#define		ep0csr10	ep0cs_addr.bit.b10	/* CLR_FORCE_STALL */
#define		ep0csr11	ep0cs_addr.bit.b11	/* CLR_SETUP_END */
#define		ep0csr12	ep0cs_addr.bit.b12	/* SEND_STALL */
#define		ep0csr13	ep0cs_addr.bit.b13	/* DATA_END_MASK */

/*------------------------------------------------------
	USB endpoint 0 max packet size register
------------------------------------------------------*/
union word_def ep0mp_addr;
#define		ep0mp	ep0mp_addr.word
#define		ep0mpl	ep0mp_addr.byte.low		/* low byte */
#define		ep0mph	ep0mp_addr.byte.high	/* high byte */

#define		wrt_cont	ep0mp_addr.bit.b7	/* Control write continuous trans mode */
#define		rd_cont		ep0mp_addr.bit.b8	/* Contorl read continuous trans mode */

/*------------------------------------------------------
	USB endpoint 0 write count register
------------------------------------------------------*/
union word_def ep0wc_addr;
#define		ep0wc		ep0wc_addr.word
#define		ep0wcl		ep0wc_addr.byte.low	/* low byte */

/*------------------------------------------------------
	USB endpoint 1 IN control/status register
------------------------------------------------------*/
union word_def ep1ics_addr;
#define		ep1ics		ep1ics_addr.word
#define		ep1icsl		ep1ics_addr.byte.low	/* low byte */
#define		ep1icsh		ep1ics_addr.byte.high	/* high byte */

#define		in1csr0		ep1ics_addr.bit.b0	/* IN_BUF_STS0 flag */
#define		in1csr1		ep1ics_addr.bit.b1	/* IN_BUF_STS1 flag */
#define		in1csr2		ep1ics_addr.bit.b2	/* UNDER-RUN flag */
#define		in1csr3		ep1ics_addr.bit.b3	/* SET_IN_BUF_RDY */
#define		in1csr4		ep1ics_addr.bit.b4	/* CLR_UNDER_RUN */
#define		in1csr5		ep1ics_addr.bit.b5	/* TOGGLE_INT */
#define		in1csr6		ep1ics_addr.bit.b6	/* FLUSH */
#define		in1csr7		ep1ics_addr.bit.b7	/* INTPT */
#define		in1csr8		ep1ics_addr.bit.b8	/* ISO */
#define		in1csr9		ep1ics_addr.bit.b9	/* SEND_STALL */
#define		in1csr10	ep1ics_addr.bit.b10	/* AUTO_SET */

/*------------------------------------------------------
	USB endpoint 1 IN max packet size registers
------------------------------------------------------*/
union word_def ep1imp_addr;
#define		ep1imp		ep1imp_addr.word
#define		ep1impl		ep1imp_addr.byte.low	/* low byte */
#define		ep1imph		ep1imp_addr.byte.high	/* high byte */

/*------------------------------------------------------
	USB endpoint 1 IN FIFO Configuration Register
------------------------------------------------------*/
union word_def ep1ifc_addr;
#define		ep1ifc		ep1ifc_addr.word
#define		ep1ifcl		ep1ifc_addr.byte.low	/* low byte */
#define		ep1ifch		ep1ifc_addr.byte.high	/* high byte */

#define		ep1i_buf_num0	ep1ifc_addr.bit.b0	/* FIFO buffer start number bit0 */
#define		ep1i_buf_num1	ep1ifc_addr.bit.b1	/* FIFO buffer start number bit1 */
#define		ep1i_buf_num2	ep1ifc_addr.bit.b2	/* FIFO buffer start number bit2 */
#define	 	ep1i_buf_num3	ep1ifc_addr.bit.b3	/* FIFO buffer start number bit3 */
#define	 	ep1i_buf_num4	ep1ifc_addr.bit.b4	/* FIFO buffer start number bit4 */
#define	 	ep1i_buf_num5	ep1ifc_addr.bit.b5	/* FIFO buffer start number bit5 */
#define	 	ep1i_buf_siz0	ep1ifc_addr.bit.b6	/* FIFO buffer size bit0 */
#define	 	ep1i_buf_siz1	ep1ifc_addr.bit.b7	/* FIFO buffer size bit1 */
#define	 	ep1i_buf_siz2	ep1ifc_addr.bit.b8	/* FIFO buffer size bit2 */
#define	 	ep1i_buf_siz3	ep1ifc_addr.bit.b9	/* FIFO buffer size bit3 */
#define	 	ep1i_dbl_buf 	ep1ifc_addr.bit.b10 /* Double buffer mode */
#define	 	ep1i_continue	ep1ifc_addr.bit.b11 /* Continuous transfer mode */

/*------------------------------------------------------
	USB endpoint 2 IN control/status register
------------------------------------------------------*/
union word_def ep2ics_addr;
#define		ep2ics		ep2ics_addr.word
#define		ep2icsl		ep2ics_addr.byte.low	/* low byte */
#define		ep2icsh		ep2ics_addr.byte.high	/* high byte */

#define		in2csr0		ep2ics_addr.bit.b0	/* IN_BUF_STS0 flag */
#define		in2csr1		ep2ics_addr.bit.b1	/* IN_BUF_STS1 flag */
#define		in2csr2		ep2ics_addr.bit.b2	/* UNDER-RUN flag */
#define		in2csr3		ep2ics_addr.bit.b3	/* SET_IN_BUF_RDY */
#define		in2csr4		ep2ics_addr.bit.b4	/* CLR_UNDER_RUN */
#define		in2csr5		ep2ics_addr.bit.b5	/* TOGGLE_INT */
#define		in2csr6		ep2ics_addr.bit.b6	/* FLUSH */
#define		in2csr7		ep2ics_addr.bit.b7	/* INTPT */
#define		in2csr8		ep2ics_addr.bit.b8	/* ISO */
#define		in2csr9		ep2ics_addr.bit.b9	/* SEND_STALL */
#define		in2csr10	ep2ics_addr.bit.b10	/* AUTO_SET */

/*------------------------------------------------------
	USB endpoint 2 IN max packet size registers
------------------------------------------------------*/
union word_def ep2imp_addr;
#define		ep2imp		ep2imp_addr.word
#define		ep2impl		ep2imp_addr.byte.low	/* low byte */
#define		ep2imph		ep2imp_addr.byte.high	/* high byte */

/*------------------------------------------------------
	USB endpoint 2 IN FIFO Configuration Register
------------------------------------------------------*/
union word_def ep2ifc_addr;
#define		ep2ifc		ep2ifc_addr.word
#define		ep2ifcl		ep2ifc_addr.byte.low	/* low byte */
#define		ep2ifch		ep2ifc_addr.byte.high	/* high byte */

#define		ep2i_buf_num0	ep2ifc_addr.bit.b0	/* FIFO buffer start number bit0 */
#define		ep2i_buf_num1	ep2ifc_addr.bit.b1	/* FIFO buffer start number bit1 */
#def