📄 mc80c7208.h
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sbit CAP2 = TM2^5 ; //
sbit T2CK2 = TM2^4 ; //
sbit T2CK1 = TM2^3 ; //
sbit T2CK0 = TM2^2 ; //
sbit T2CN = TM2^1 ; //
sbit T2ST = TM2^0 ; //
sfr T2 = 0xD7 ; // [R] Timer2 Reg.
sfr TDR2 = 0xD7 ; // [W] Timer2 Data Reg.
sfr CDR2 = 0xD7 ; // [R] Timer2 Capture Data Reg.
sfr TM3 = 0xD8 ; // [R/W] Timer3 Mode Control Reg.
sbit POL3 = TM3^7 ; //
sbit T16B3 = TM3^6 ; //
sbit PWM1E = TM3^5 ; //
sbit T3CK1 = TM3^3 ; //
sbit T3CK0 = TM3^2 ; //
sbit T3CN = TM3^1 ; //
sbit T3ST = TM3^0 ; //
sfr TDR3 = 0xD9 ; // [W] Timer3 Data Reg.
sfr T3PPR = 0xD9 ; // [W] Timer3 PWM Period Reg.
sfr T3 = 0xDA ; // [R] Timer3 Reg.
sfr T3PDR = 0xDA ; // [R/W] Timer3 PWM Duty Reg.
sfr CDR3 = 0xDA ; // [R] Timer3 Capture Data Reg.
sfr T3PWHR = 0xDB ; // [W] Timer3 PWM High Reg.
sfr ADCM = 0xE2 ; // [R/W] 8 bitADC Mode Control Reg.
sbit ADEN = ADCM^6 ; // AD Converter Enable[1]/Disable[0]
sbit ADS2 = ADCM^4 ; // Analog Input Port Select
sbit ADS1 = ADCM^3 ; //
sbit ADS0 = ADCM^2 ; //
sbit ADST = ADCM^1 ; // AD Converter Start[1]
sbit ADSF = ADCM^0 ; // [R] AD Conversion Completed[1]/Busy[1]
sfr ADCR = 0xE3 ; // [R] 10bit ADC Data Low Reg. (8bit)
sfr PFDR = 0xE5 ; // [R/W] PFD Control Reg.
sbit PFDE = PFDR^7 ; // PFD Enable
sbit SEL_HL = PFDR^6 ; // PFD_out Selection
sbit PFDMS1 = PFDR^5 ; // PFD Mode Selection
sbit PFDMS0 = PFDR^4 ; //
sbit PFDF1 = PFDR^1 ; // PFD High Detection Flag
sbit PFDF0 = PFDR^0 ; // PFD Low Detection Flag
sfr BITR = 0xE6 ; // [R] Basic Interval Timer Reg.
sfr CKCTLR = 0xE6 ; // [W] Clock Control Reg.
sfr SCMR = 0xE7 ; // [R/W] System Clock Model Reg.
sbit MCC = SCMR^2 ; // Main System Clock Stop[1]
sbit CS1 = SCMR^1 ; // System Clock Select
sbit CS0 = SCMR^0 ; //
sfr WDTR = 0xE8 ; // [W] Watchdog Timer Reg.
sfr WDTDR = 0xE8 ; // [R] Watchdog Timer Reg.
sfr WTR = 0xE8 ; // [W] Watch Timer Reg.
sfr SSCR = 0xE9 ; // [W] Stop & Sleep Mode Control Reg.
sfr WTMR = 0xEA ; // [R/W] Watch Timer Mode Reg.
sbit WTEN = WTMR^7 ; // Watch Timer enable
sbit LOADEN = WTMR^6 ; // 7bit Reload Counter Write Enable
sbit WTIN1 = WTMR^3 ; // Interrupt Interval Selection
sbit WTIN0 = WTMR^2 ; //
sbit WTCK1 = WTMR^1 ; // Clock Source Selection
sbit WTCK0 = WTMR^0 ; //
sfr KSMR = 0xEB ; // [R/W] Key Scan Mode Reg.
sfr CFHS = 0xEC ; // [W] Carrier Frequency High Reg.
sfr CFLS = 0xED ; // [W] Carrier Frequency Low Reg.
sfr RMR = 0xEE ; // [R/W] Remocon Mode Reg.
sbit REN = RMR^6 ; // Remocon Operating Enable
sbit CCK1 = RMR^5 ; // Carrier Clock Source Select
sbit CCK0 = RMR^4 ; //
sbit RDPE = RMR^3 ; // Remocon Data Pulse Enable
sbit RDCK2 = RMR^2 ; // Remocon Data Clock Selection
sbit RDCK1 = RMR^1 ; //
sbit RDCK0 = RMR^0 ; //
sfr RDHR = 0xEF ; // [W] Remocon Data High Reg.
sfr RDLR = 0xF0 ; // [W] Remocon Data Low Reg.
sfr RDC = 0xF1 ; // [R] Remocon Data Counter Reg.
sfr RODR = 0xF2 ; // [R/W] Remocon Output Data Reg.
sbit ROD0 = RODR^0 ; //
sfr ROB = 0xF3 ; // [R/W] Remocon Output Buffer
sbit ROB0 = ROB^0 ; //
sfr INTFL = 0xF5 ; // [R/W] Interrupt Generation Flag Low Reg.
sbit T2F = INTFL^7 ; // Timer2 INT Flag
sbit T3F = INTFL^6 ; // Timer3 INT Flag
sbit ADCF = INTFL^2 ; // ADC INT Flag
sbit WTF = INTFL^1 ; // Watch Timer INT Flag
sbit WDTF = INTFL^0 ; // Watchdog Timer INT Flag
sfr IENH = 0xF6 ; // [R/W] Interrupt Enable High Reg.
sbit KSE = IENH^7 ; // Key Scan Int Enable
sbit INT0E = IENH^6 ; // External INT0 Enable
sbit INT1E = IENH^5 ; // External INT1 Enable
sbit RX0E = IENH^3 ; // UART0 RX INT Enable
sbit TX0E = IENH^2 ; // UART0 TX INT Enable
sfr IENM = 0xF7 ; // [R/W] Interrupt Enable Low Reg.
sbit T0E = IENM^7 ; // Timer/Counter 0 INT Enable
sbit T1E = IENM^6 ; // Timer/Counter 1 INT Enable
sbit T2E = IENM^5 ; // Timer/Counter 2 INT Enable
sbit T3E = IENM^4 ; // Timer/Counter 3 INT Enable
sbit CGE = IENM^1 ; // Carrier Generater INT Enable
sbit ADCE = IENM^0 ; // ADC INT Enable
sfr IENL = 0xF8 ; // [R/W] Interrupt Enable Low Reg.
sbit BITE = IENL^6 ; // Basic Interval Timer INT Enable
sbit WDTE = IENL^5 ; // Watchdog Timer INT Enable
sbit WTE = IENL^4 ; // Watch Timer INT Enable
sfr IRQH = 0xF9 ; // [R/W] Interrupt Request High Reg.
sbit KSIF = IRQH^7 ; // Key Scan Int Request
sbit INT0IF = IRQH^6 ; // External INT0 Request
sbit INT1IF = IRQH^5 ; // External INT1 Request
sbit RX0IF = IRQH^3 ; // UART0 RX INT Request
sbit TX0IF = IRQH^2 ; // UART0 TX INT Request
sfr IRQM = 0xFA ; // [R/W] Interrupt Request Low Reg.
sbit T0IF = IRQM^7 ; // Timer/Counter 0 INT Request
sbit T1IF = IRQM^6 ; // Timer/Counter 1 INT Request
sbit T2IF = IRQM^5 ; // Timer/Counter 2 INT Request
sbit T3IF = IRQM^4 ; // Timer/Counter 3 INT Request
sbit CGIF = IRQM^1 ; // Carrier Generator INT Request
sbit ADCIF = IRQM^0 ; // ADC INT Request
sfr IRQL = 0xFB ; // [R/W] Interrupt Request Low Reg.
sbit BITIF = IRQL^6 ; // Basic Interval Timer INT Request
sbit WDTIF = IRQL^5 ; // Watchdog Timer INT Request
sbit WTIF = IRQL^4 ; // Watch Timer INT Request
sfr IEDS = 0xFC ; // [W] Interrupt Enable Edge Reg.
sbit IED1H = IEDS^3 ; //
sbit IED1L = IEDS^2 ; //
sbit IED0H = IEDS^1 ; //
sbit IED0L = IEDS^0 ; //
sfr SEG0 = 0x0460 ;
sfr SEG1 = 0x0461 ;
sfr SEG2 = 0x0462 ;
sfr SEG3 = 0x0463 ;
sfr SEG4 = 0x0464 ;
sfr SEG5 = 0x0465 ;
sfr SEG6 = 0x0466 ;
sfr SEG7 = 0x0467 ;
sfr SEG8 = 0x0468 ;
sfr SEG9 = 0x0469 ;
sfr SEG10 = 0x046A ;
sfr SEG11 = 0x046B ;
sfr SEG12 = 0x046C ;
sfr SEG13 = 0x046D ;
sfr SEG14 = 0x046E ;
sfr SEG15 = 0x046F ;
sfr SEG16 = 0x0470 ;
sfr SEG17 = 0x0471 ;
sfr SEG18 = 0x0472 ;
sfr SEG19 = 0x0473 ;
sfr SEG20 = 0x0474 ;
sfr SEG21 = 0x0475 ;
sfr SEG22 = 0x0476 ;
sfr SEG23 = 0x0477 ;
sfr SEG32 = 0x0480 ;
sfr SEG33 = 0x0481 ;
sfr SEG34 = 0x0482 ;
#endif // _MC80C7208_H_
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