📄 mc80c7208.h
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// Title ; Control Registers Definitions of MC80C7208
// File Name : MC80C7208.h (64 MQFP/LQFP)
// Release Date : 2005.06.28.
// Revision No. : 1.1
// Programmer : Byoung-jin Lim
// Checked by : SungJae Hwang
/* Copyright (c) 2005 MagnaChip Semiconductor Ltd.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
History
1. 05-01-07 SMR appended
*/
#ifndef _MC80C7208_H_
#define _MC80C7208_H_ 1
sfr R0OD = 0xA0 ; // [W] R0 Open Drain Control Reg.
sfr R1OD = 0xA1 ; // [W] R1 Open Drain Control Reg.
sfr R2OD = 0xA2 ; // [W] R2 Open Drain Control Reg.
sfr R3OD = 0xA3 ; // [W] R3 Open Drain Control Reg.
sfr R0PU = 0xA5 ; // [W] R0 Pull up Reg.
sfr R1PU = 0xA6 ; // [W] R1 Pull up Reg.
sfr R2PU = 0xA7 ; // [W] R2 Pull up Reg.
sfr R3PU = 0xA8 ; // [W] R3 Pull up Reg.
sfr R0FUNC = 0xAA ; // [W] R0 Function select Reg.
sfr R1FUNC = 0xAB ; // [W] R1 Function select Reg.
sfr R5PSR = 0xAC ; // [R/W] R5/LCD Port Selection Reg.
sfr R6PSR = 0xAD ; // [R/W] R6/LCD Port Selection Reg.
sfr R7PSR = 0xAE ; // [R/W] R7/LCD Port Selection Reg.
sfr R7 = 0xB0 ; // [R/W] R7 Port Reg.
sfr LCR = 0xB2 ; // [R/W] LCD Control Reg.
sbit SCKD = LCR^7 ; // Sub Clock Disable[1]
sbit REFENB = LCR^6 ; // LCD Power Select(Internal,External)
sbit LCDEN = LCR^5 ; // LCD Display Enable
sbit VBEN = LCR^4 ; // Voltage Boostet Enable
sbit LCDD1 = LCR^3 ; // LCD Duty Selection
sbit LCDD0 = LCR^2 ; //
sbit LCK1 = LCR^1 ; // LCD Clock Source Selection
sbit LCK0 = LCR^0 ; //
sfr ASIMR0 = 0xB8 ; // [R/W] Asynchronus Serial Interface Mode0 Reg. for MC80F7X08 only
sbit TX0M = ASIMR0^7; // Operation Mode
sbit RX0M = ASIMR0^6; //
sbit PS01 = ASIMR0^5; // Parity Bit Selection
sbit PS00 = ASIMR0^4; //
sbit SL0 = ASIMR0^2; // Stop Bit Length
sbit ISRM0 = ASIMR0^1; // Receive Completion Interrupt Request
sfr ASISR0 = 0xB9 ; // [R] Asynchronus Serial Interface Status0 Reg. for MC80F7X08 only
sbit PE0 = ASISR0^2; // Parity Error
sbit FE0 = ASISR0^1; // Framing Error
sbit OVE0 = ASISR0^0; // Overrun Error
sfr BRGCR0 = 0xBA ; // [R/W] BAUD rate generate control 0 Reg. for MC80F7X08 only
sbit TPS2 = LCR^6 ; // Source Clock Selection for 5-bit Counter
sbit TPS1 = LCR^5 ; //
sbit TPS0 = LCR^4 ; //
sbit MDL3 = LCR^3 ; // Input Clock Selection for Baud Rate Generator
sbit MDL2 = LCR^2 ; //
sbit MDL1 = LCR^1 ; //
sbit MDL0 = LCR^0 ; //
sfr RXBR0 = 0xBB ; // [R] Receiver Buffer 0 Reg. for MC80F7X08 only
sfr TXSR0 = 0xBB ; // [W] Transmit Shift 0 Reg. for MC80F7X08 only
sfr R0 = 0xC0 ; // [R/W] R0 Port Data Reg.
sbit R07 = R0^7 ; // INT1
sbit R06 = R0^6 ; // INT0
sbit R04 = R0^4 ; // BUZ
sbit R01 = R0^1 ; // EC0
sfr R0IO = 0xC1 ; // [W] R0 Port Direction Reg.
sfr R1 = 0xC2 ; // [R/W] R1 Port Data Reg.
sbit R10 = R1^0 ;
sfr R1IO = 0xC3 ; // [W] R1 Port Direction Reg.
sfr R2 = 0xC4 ; // [R/W] R2 Port Data Reg.
sbit R25 = R2^5 ;
sbit R24 = R2^4 ;
sbit R23 = R2^3 ;
sbit R22 = R2^2 ;
sbit R21 = R2^1 ;
sbit R20 = R2^0 ;
sfr R2IO = 0xC5 ; // [W] R2 Port Direction Reg.
sfr R3 = 0xC6 ; // [R/W] R3 Port Data Reg.
sbit R37 = R3^7 ;
sbit R36 = R3^6 ;
sbit R35 = R3^5 ;
sbit R34 = R3^4 ;
sfr R3IO = 0xC7 ; // [W] R3 Port Direction Reg.
sfr R5 = 0xCA ; // [R/W] R5 Port Data Reg.
sbit R57 = R5^7 ;
sbit R56 = R5^6 ;
sbit R55 = R5^5 ;
sbit R54 = R5^4 ;
sbit R53 = R5^3 ;
sbit R52 = R5^2 ;
sbit R51 = R5^1 ;
sbit R50 = R5^0 ;
sfr R5IO = 0xCB ; // [W] R5 Port Direction Reg.
sfr R6 = 0xCC ; // [R/W] R6 Port Data Reg.
sbit R67 = R6^7 ;
sbit R66 = R6^6 ;
sbit R65 = R6^5 ;
sbit R64 = R6^4 ;
sbit R63 = R6^3 ;
sbit R62 = R6^2 ;
sbit R61 = R6^1 ;
sbit R60 = R6^0 ;
sfr R6IO = 0xCD ; // [W] R6 Port Direction Reg.
sfr BUZR = 0xCE ; // [W] Buzzer Driver Reg.
sfr RPR = 0xCF ; // [R/W] RAM Page Reg.
sfr TM0 = 0xD0 ; // [R/W] Timer0 Mode Control Reg.
sbit CAP0 = TM0^5 ; // Timer0
sbit T0CK2 = TM0^4 ; // Timer0 Clock Select
sbit T0CK1 = TM0^3 ; //
sbit T0CK0 = TM0^2 ; //
sbit T0CN = TM0^1 ; //
sbit T0ST = TM0^0 ; //
sfr T0 = 0xD1 ; // [R] Timer0 Reg.
sfr TDR0 = 0xD1 ; // [W] Timer0 Data Reg.
sfr CDR0 = 0xD1 ; // [R] Timer0 Capture Data Reg.
sfr TM1 = 0xD2 ; // [R/W] Timer1 Mode Control Reg.
sbit T16B1 = TM1^6 ; //
sbit T1CK1 = TM1^3 ; //
sbit T1CK0 = TM1^2 ; //
sbit T1CN = TM1^1 ; //
sbit T1ST = TM1^0 ; //
sfr TDR1 = 0xD3 ; // [W] Timer1 Data Reg.
sfr T1 = 0xD4 ; // [R] Timer1 Reg.
sfr CDR1 = 0xD4 ; // [R] Timer1 Capture Data Reg.
sfr TM2 = 0xD6 ; // [R/W] Timer2 Mode Control Reg.
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