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<TD class=bold width="75%">标题: 如何计算门数</TD>
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<TD class=bold align=middle colSpan=2> 本主题由 <A
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2005-10-6 17:14 设置高亮 </TD></TR>
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style="FONT-SIZE: 12px">请问各位高手，如何计算你的片子用的门数呀？</SPAN>
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<TD align=left>2005-1-14 17:32</TD>
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class=bold>如何计算门数</SPAN></SPAN><BR><BR><SPAN
style="FONT-SIZE: 12px">一般来说，FPGA/CPLD说的是用了多少CLB或slice，具体的门数只是个估计值，我是这么看的。在ISE中实现后，会有Map
Report和Post P&R Static Timing Report，你只要看Map
Report中的信息就可以了，比如我的设计给出的Map Report是这样的：<BR>Number of
errors: 0<BR>Number of
warnings: 5<BR>Logic
Utilization:<BR> Number of Slice Flip Flops:
1,278 out of 3,072
41%<BR> Number of 4 input LUTs:
1,172 out of
3,072 38%<BR>Logic
Distribution:<BR> Number of occupied Slices:
959 out of
1,536 62%<BR> Number of Slices
containing only related logic: 959 out
of
959 100%<BR> Number of
Slices containing unrelated logic:
0 out of 959
0%<BR> *See NOTES
below for an explanation of the effects of unrelated
logic<BR>Total Number 4 input LUTs:
1,237 out of 3,072
40%<BR> Number used as logic:
1,172<BR> Number used as a route-thru:
65<BR> Number of
bonded IOBs:
40 out of 92
43%<BR> IOB Flip Flops:
1<BR> Number of Block
RAMs:
6 out of
24 25%<BR> Number of GCLKs:
3 out of
16 18%<BR>Total equivalent gate count for
design: 414,573 //这就是门数<BR>Additional
JTAG gate count for IOBs: 1,920<BR>Peak Memory
Usage: 86 MB</SPAN> </TD></TR></TBODY></TABLE></TD></TR>
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