mac.vhd

Xilinx高级试验的代码.zip 非常不错

library ieee;
use ieee.std_logic_1164.all;

entity mac is
    
    port (
        clk, reset, dv_enable                              : in  std_logic;
        data_valid                                         : in  std_logic_vector (3 downto 0);
        rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd : in  std_logic_vector (7 downto 0);
        mac_cha, mac_chb, mac_chc, mac_chd                 : out std_logic_vector (20 downto 0);
        mac_dv                                             : out std_logic_vector (3 downto 0));

end mac;

architecture structure of mac is
    component mac_ch is
    port (
        clk, reset, data_valid, dv_enable : in  std_logic;
        data_ch                           : in  std_logic_vector (7 downto 0);
        mac_data_valid                    : out std_logic;
        mac_data                          : out std_logic_vector (20 downto 0));
    end component mac_ch;

begin  -- structure

    mac_cha_inst: mac_ch
        port map(clk => clk,
                 reset => reset,
                 data_valid => data_valid(0),
                 dv_enable => dv_enable,
                 data_ch => rd_data_cha,
                 mac_data_valid => mac_dv(0),
                 mac_data => mac_cha);

        mac_chb_inst: mac_ch
        port map(clk => clk,
                 reset => reset,
                 data_valid => data_valid(1),
                 dv_enable => dv_enable,
                 data_ch => rd_data_chb,
                 mac_data_valid => mac_dv(1),
                 mac_data => mac_chb);

    mac_chc_inst: mac_ch
        port map(clk => clk,
                 reset => reset,
                 data_valid => data_valid(2),
                 dv_enable => dv_enable,
                 data_ch => rd_data_chc,
                 mac_data_valid => mac_dv(2),
                 mac_data => mac_chc);

    mac_chd_inst: mac_ch
        port map(clk => clk,
                 reset => reset,
                 data_valid => data_valid(3),
                 dv_enable => dv_enable,
                 data_ch => rd_data_chd,
                 mac_data_valid => mac_dv(3),
                 mac_data => mac_chd);

end structure;