mac_ch.v

Xilinx高级试验的代码.zip 非常不错

module mac_ch (clk, reset, data_valid, data_ch, mac_data, mac_data_valid, dv_enable);
    input clk, reset, data_valid, dv_enable;
    input [7:0] data_ch;
    output 	mac_data_valid;
    output [20:0] mac_data;
    reg [20:0] mac_data;

    reg [3:0] 	  dv;
    reg [7:0]  accumulator_cntr;
    integer    product, accumulator;
    reg [7:0] data_ch_q0;
    reg      data_sign;
    
    reg       data_valid_q0;

    parameter K = -30;

    assign    mac_data_valid = | dv; // hold for four clock cycles (multi-cycle output path)
        
    always @ (posedge clk or posedge reset)
    begin
	if (reset)
	begin
	    data_sign <= 0;
	    dv <= 0;
	    mac_data <= 0;
	    data_valid_q0 <= 0;
	    data_ch_q0 <= 0;
	    accumulator <= 0;
	    accumulator_cntr <= 0;
	end // if (reset)
	else
	begin
	    // defaults

	    if (dv_enable)
	    begin
		data_valid_q0 <= data_valid;
		dv <= {1'b0, dv[3:1]};
		data_sign <= data_ch[7];
		
		if (data_ch[7])
		  data_ch_q0 <= -data_ch; // 2's compliment
		else
		  data_ch_q0 <= data_ch;
	    end
		
	    if (data_valid_q0 & dv_enable)
	    begin
		

		accumulator_cntr <= accumulator_cntr + 1;
		product = K * data_ch_q0; // remains combinatorial
		if (data_sign)
		  accumulator <= accumulator - product;
		else
		  accumulator <= accumulator + product;
		
		if (accumulator_cntr == 255)
		begin
		    accumulator_cntr <= 0;
		    dv[3] <= 1;
		    mac_data <= accumulator;
		    accumulator <= 0;
		end // if (accumulator_cntr == 255)
	    end // if (data_valid_q0)
		
	end // else: !if(reset)
    end // always @ (posedge clk or posedge reset)

endmodule // mac_ch