synth_lab.npl

Xilinx高级试验的代码.zip 非常不错

JDF F
// Created by Project Navigator ver 1.0
PROJECT synth_lab
DESIGN synth_lab Normal
DEVFAM virtex2
DEVFAMTIME 1029799323
DEVICE xc2v250
DEVICETIME 1029799323
DEVPKG fg256
DEVPKGTIME 1029799323
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 1027535485
MODULE ..\data_control_fsm.v
MODSTYLE data_control_fsm Normal
MODULE ..\data_output_mux.v
MODSTYLE data_output_mux Normal
MODULE ..\mac.v
MODSTYLE mac Normal
MODULE ..\mac_ch.v
MODSTYLE mac_ch Normal
MODULE ..\data_control.v
MODSTYLE data_control Normal
MODULE ..\read_ch_arbiter.v
MODSTYLE read_ch_arbiter Normal
[STRATEGY-LIST]
Normal=True