correlate_and_accumulate.vhd

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library ieee;
use ieee.std_logic_1164.all;
-- synopsys translate_off
library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
-- synopsys translate_on

entity correlate_and_accumulate is
    generic (
        Ka : std_logic_vector (7 downto 0) := "10001101";
        Kb : std_logic_vector (7 downto 0) := "11100101";
        Kc : std_logic_vector (7 downto 0) := "00101110";
        Kd : std_logic_vector (7 downto 0) := "11010001");
    port (
        rd_clk, wr_clk_cha, wr_clk_chb, wr_clk_chc, reset,
        wr_clk_chd, data_cha, data_chb, data_chc, data_chd : in  std_logic;
        final_data                                         : out std_logic_vector(7 downto 0);
        mac_cha, mac_chb, mac_chc, mac_chd                 : out std_logic_vector (20 downto 0);
        mac_dv                                             : out std_logic_vector (3 downto 0);
        valid_ch                                           : out std_logic_vector (3 downto 0));
end correlate_and_accumulate;

architecture structure of correlate_and_accumulate is

    component data_control is
        port (
            clk, reset                                                      : in  std_logic;
            rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd              : in  std_logic_vector (7 downto 0);
            pn_lock_rd_clk, almost_full, almost_empty, full, empty      : in  std_logic_vector(3 downto 0);
            rd, valid_ch, mac_dv                                            : out std_logic_vector (3 downto 0);
            final_data                                                      : out std_logic_vector (7 downto 0);
            mac_cha, mac_chb, mac_chc, mac_chd                              : out std_logic_vector (20 downto 0));
    end component data_control;

    component ch_fifo is
        generic (
            K : std_logic_vector (7 downto 0) := "10001101");
        port (
            rd_clk, wr_clk, reset, data_ch, rd                     : in  std_logic;
            pn_lock_rd_clk, almost_full, almost_empty, full, empty : out std_logic;
            rd_data                                                : out std_logic_vector (7 downto 0));
    end component ch_fifo;

    component bufgdll
        port (
            i : in  std_logic;
            o : out std_logic);
    end component;
    
    signal rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd : std_logic_vector (7 downto 0);
    signal rd, pn_lock_rd_clk, almost_full, almost_empty, full, empty : std_logic_vector (3 downto 0);
    signal rd_clk_dll, wr_clka_dll, wr_clkb_dll, wr_clkc_dll, wr_clkd_dll : std_logic;
begin  -- structure
    
    rd_clk_inst: bufgdll port map(i => rd_clk, o => rd_clk_dll);
    wr_clk_cha_inst: bufgdll port map(i => wr_clk_cha, o => wr_clka_dll);
    wr_clk_chb_inst: bufgdll port map(i => wr_clk_chb, o => wr_clkb_dll);
    wr_clk_chc_inst: bufgdll port map(i => wr_clk_chc, o => wr_clkc_dll);
    wr_clk_chd_inst: bufgdll port map(i => wr_clk_chd, o => wr_clkd_dll);
    
    data_control_inst : data_control
        port map(
            clk => rd_clk_dll,
            reset => reset,
            rd_data_cha => rd_data_cha,
            rd_data_chb => rd_data_chb,
            rd_data_chc => rd_data_chc,
            rd_data_chd => rd_data_chd,
            pn_lock_rd_clk => pn_lock_rd_clk,
            almost_full => almost_full,
            almost_empty => almost_empty,
            full => full,
            empty => empty,
            rd => rd,
            valid_ch => valid_ch,
            mac_dv => mac_dv,
            final_data => final_data,
            mac_cha => mac_cha,
            mac_chb => mac_chb,
            mac_chc => mac_chc,
            mac_chd => mac_chd);
    
    cha_fifo_inst: ch_fifo
        generic map (
            K => Ka)
        port map(
            rd_clk => rd_clk_dll,
            wr_clk => wr_clka_dll,
            reset => reset,
            data_ch => data_cha,
            rd => rd(0),
            pn_lock_rd_clk => pn_lock_rd_clk(0),
            almost_full => almost_full(0),
            almost_empty => almost_empty(0),
            full => full(0),
            empty => empty(0),
            rd_data => rd_data_cha);

        chb_fifo_inst: ch_fifo
        generic map (
            K => Kb)
        port  map(
            rd_clk => rd_clk_dll,
            wr_clk => wr_clkb_dll,
            reset => reset,
            data_ch => data_chb,
            rd => rd(1),
            pn_lock_rd_clk => pn_lock_rd_clk(1),
            almost_full => almost_full(1),
            almost_empty => almost_empty(1),
            full => full(1),
            empty => empty(1),
            rd_data => rd_data_chb);

    chc_fifo_inst: ch_fifo
        generic map (
            K => Kc)
        port  map(
            rd_clk => rd_clk_dll,
            wr_clk => wr_clkc_dll,
            reset => reset,
            data_ch => data_chc,
            rd => rd(2),
            pn_lock_rd_clk => pn_lock_rd_clk(2),
            almost_full => almost_full(2),
            almost_empty => almost_empty(2),
            full => full(2),
            empty => empty(2),
            rd_data => rd_data_chc);

    chd_fifo_inst: ch_fifo
        generic map (
            K => Kd)
        port  map(
            rd_clk => rd_clk_dll,
            wr_clk => wr_clkd_dll,
            reset => reset,
            data_ch => data_chd,
            rd => rd(3),
            pn_lock_rd_clk => pn_lock_rd_clk(3),
            almost_full => almost_full(3),
            almost_empty => almost_empty(3),
            full => full(3),
            empty => empty(3),
            rd_data => rd_data_chd);
       
end structure;