coregen_lab.npl

Xilinx高级试验的代码.zip 非常不错

JDF F
// Created by Project Navigator ver 1.0
PROJECT coregen_lab
DESIGN coregen_lab Normal
DEVFAM virtex2
DEVFAMTIME 1029799202
DEVICE xc2v250
DEVICETIME 1029799202
DEVPKG fg256
DEVPKGTIME 1029799202
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 1027535667
STIMULUS ..\fifo_2048x8_tb.vhd Normal
MODULE ..\fifo_2048x8.vhd
MODSTYLE fifo_2048x8 Normal
MODULE ..\pn_correlation.vhd
MODSTYLE pn_correlation Normal
MODULE ..\read_ch_arbiter.vhd
MODSTYLE read_ch_arbiter Normal
MODULE ..\pn_correlation_fsm.vhd
MODSTYLE pn_correlation_fsm Normal
MODULE ..\correlate_and_accumulate.vhd
MODSTYLE correlate_and_accumulate Normal
MODULE ..\data_output_mux.vhd
MODSTYLE data_output_mux Normal
MODULE ..\pn_correlator.vhd
MODSTYLE pn_correlator Normal
MODULE ..\data_control.vhd
MODSTYLE data_control Normal
MODULE ..\mac_ch.vhd
MODSTYLE mac_ch Normal
MODULE ..\fifo_status.vhd
MODSTYLE fifo_status Normal
MODULE ..\data_control_fsm.vhd
MODSTYLE data_control_fsm Normal
MODULE ..\mac.vhd
MODSTYLE mac Normal
MODULE ..\ch_fifo.vhd
MODSTYLE ch_fifo Normal
LIBFILE ..\correlate_and_accumulate_pack.vhd work ***
[STRATEGY-LIST]
Normal=True