data_output_mux.vhd

Xilinx高级试验的代码.zip 非常不错

library ieee;
use ieee.std_logic_1164.all;

entity data_output_mux is
    
    port (
        clk, reset, dv_enable : in std_logic;
        data_valid : in std_logic_vector (3 downto 0);
        data_cha, data_chb, data_chc, data_chd : in std_logic_vector (7 downto 0);
        final_data : out std_logic_vector (7 downto 0);
        valid_ch : out std_logic_vector (3 downto 0));

end data_output_mux;

architecture rtl of data_output_mux is
    type v_ch_array is array (3 downto 0) of std_logic_vector(3 downto 0);
    signal v_ch : v_ch_array;
begin  -- rtl

    valid_ch <= v_ch(3) or v_ch(2) or v_ch(1) or v_ch(0);

    process (clk, reset)
    begin  -- process
        if reset = '1' then
            for i in 3 downto 0 loop
                v_ch(i) <= (others => '0');
            end loop;  -- i
            final_data <= (others => '0');
        elsif rising_edge(clk) then
            v_ch(3) <= (others => '0');
            v_ch(2 downto 0) <= v_ch(3 downto 1);

            if dv_enable = '1' then
                v_ch(3) <= data_valid;
                case data_valid is
                    when "0001" =>
                        final_data <= data_cha;
                    when "0010" =>
                        final_data <= data_chb;
                    when "0100" =>
                        final_data <= data_chc;
                    when "1000" =>
                        final_data <= data_chd;
                    when others => null;
                end case;
            end if;
        end if;
        
    end process;
    
    

end rtl;