fifo_ver.do

来自「Xilinx高级试验的代码.zip 非常不错」· DO 代码 · 共 14 行

vlib work
vlog -93 -y . +libext+.v+.ve+ +define+OVI_Verilog+   ram_core.v
vlog -93 -y . +libext+.v+.ve+ +define+OVI_Verilog+   ../fifo_2048x8.v
vlog -93 -y . +libext+.v+.ve+ +define+OVI_Verilog+   y:/Xili/FISE_4_1/verilog/src/glbl.v
vlog -93 -y . +libext+.v+.ve+ +define+OVI_Verilog+   fifo_2048x8_tb.tf
set desunit "fifo_2048x8_tb"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver -lib work $desunit glbl
do fifo_2048x8_tb.udo
view wave
add wave *
view structure
view signals
run 2000ns