📄 fifo_2048x8_tb.tf
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`timescale 1 ns / 1 ns
module fifo_2048x8_tb;
reg rd_clk, wr_clk, reset, wr, rd;
reg [10:0] wr_addr, rd_addr;
reg [7:0] wr_data;
reg [7:0] misc_data [0:15];
wire [7:0] rd_data;
reg done_writing;
integer i,j;
fifo_2048x8 fifo_2048x8_inst
(.rd_clk(rd_clk),
.wr_clk(wr_clk),
.wr(wr),
.rd(rd),
.reset(reset),
.wr_addr(wr_addr),
.rd_addr(rd_addr),
.wr_data(wr_data),
.rd_data(rd_data));
initial
begin
misc_data[0] = 8'h00;
misc_data[1] = 8'h01;
misc_data[2] = 8'h02;
misc_data[3] = 8'h03;
misc_data[4] = 8'h04;
misc_data[5] = 8'h05;
misc_data[6] = 8'h06;
misc_data[7] = 8'h07;
misc_data[8] = 8'h08;
misc_data[9] = 8'h09;
misc_data[10] = 8'h0a;
misc_data[11] = 8'h0b;
misc_data[12] = 8'h0c;
misc_data[13] = 8'h0d;
misc_data[14] = 8'h0e;
misc_data[15] = 8'h0f;
reset = 1;
rd_clk = 0;
wr_clk = 1;
rd = 0;
wr = 0;
done_writing = 0;
wr_data = 0;
rd_addr = 0;
wr_addr = 0;
#27 reset = 0;
end // initial begin
always #2.5 rd_clk = ~rd_clk;
always #5 wr_clk = ~wr_clk;
always
begin
@ (negedge reset);
for (i = 0; i <= 15; i = i + 1)
begin
wr_data <= misc_data[i];
wr_addr <= i;
for (j = 0; j <= 7; j = j + 1)
begin
if (j == 7)
wr <= 1;
else
wr <= 0;
@ (posedge wr_clk);
end // for (j = 0; j <= 7; j = j + 1)
end // for (i = 0; i <= 15; i = i + 1)
done_writing = 1;
wr <= 0;
@ (posedge wr_clk);
end // always begin
always
begin
@ (negedge reset);
@ (posedge done_writing);
for (i = 0; i <= 15; i = i + 1)
begin
rd_addr <= i;
for (j = 0; j <= 7; j = j + 1)
begin
if (j == 7)
rd <= 1;
else
rd <= 0;
@ (posedge rd_clk);
end // for (j = 0; j <= 7; j = j + 1)
end // for (i = 0; i <= 15; i = i + 1)
rd <= 0;
@ (posedge rd_clk);
#100 $stop;
end // always begin
endmodule // fifo_2048x8_tb
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