coregen_lab.npl

来自「Xilinx高级试验的代码.zip 非常不错」· NPL 代码 · 共 44 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT coregen_lab
DESIGN coregen_lab Normal
DEVFAM virtex2
DEVFAMTIME 1029799173
DEVICE xc2v250
DEVICETIME 1029799173
DEVPKG fg256
DEVPKGTIME 1029799173
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 1027535629
STIMULUS ..\fifo_2048x8_tb.tf Normal
MODULE ..\pn_correlation.v
MODSTYLE pn_correlation Normal
MODULE ..\pn_correlation_fsm.v
MODSTYLE pn_correlation_fsm Normal
MODULE ..\data_output_mux.v
MODSTYLE data_output_mux Normal
MODULE ..\pn_correlator.v
MODSTYLE pn_correlator Normal
MODULE ..\correlate_and_accumulate.v
MODSTYLE correlate_and_accumulate Normal
MODULE ..\fifo_status.v
MODSTYLE fifo_status Normal
MODULE ..\data_control.v
MODSTYLE data_control Normal
MODULE ..\mac_ch.v
MODSTYLE mac_ch Normal
MODULE ..\mac.v
MODSTYLE mac Normal
MODULE ..\data_control_fsm.v
MODSTYLE data_control_fsm Normal
MODULE ..\ch_fifo.v
MODSTYLE ch_fifo Normal
MODULE ..\fifo_2048x8.v
MODSTYLE fifo_2048x8 Normal
MODULE ..\read_ch_arbiter.v
MODSTYLE read_ch_arbiter Normal
[STRATEGY-LIST]
Normal=True