correlate_and_accumulate.v

Xilinx高级试验的代码.zip 非常不错

module correlate_and_accumulate (wr_clk_cha, wr_clk_chb, wr_clk_chc, wr_clk_chd, rd_clk, reset, data_cha, 
				 data_chb, data_chc, data_chd, final_data, valid_ch, mac_cha, mac_chb, mac_chc,
				 mac_chd, mac_dv);
    input wr_clk_cha, wr_clk_chb, wr_clk_chc, wr_clk_chd, rd_clk, reset;
    input data_cha, data_chb, data_chc, data_chd;
    output [7:0] final_data;
    output [3:0] valid_ch;
    output [20:0] mac_cha, mac_chb, mac_chc, mac_chd;
    output [3:0]	  mac_dv;

    wire [7:0] 	  rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd;
    wire [3:0] 	  rd, pn_lock_rd_clk, almost_full, almost_empty, full, empty;
    wire 	  rd_clk_dll, wr_clka_dll, wr_clkb_dll, wr_clkc_dll, wr_clkd_dll;

    defparam 	 cha_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b10001101;
    defparam 	 chb_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b11100101;
    defparam 	 chc_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b00101110; 
    defparam 	 chd_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b11010001;
    
    data_control data_control_inst
      (.clk(rd_clk_dll), 
       .reset(reset), 
       .pn_lock_rd_clk(pn_lock_rd_clk), 
       .rd_data_cha(rd_data_cha), 
       .rd_data_chb(rd_data_chb), 
       .rd_data_chc(rd_data_chc), 
       .rd_data_chd(rd_data_chd), 
       .rd(rd), 
       .final_data(final_data), 
       .almost_full(almost_full),
       .almost_empty(almost_empty),
       .full(full),
       .empty(empty),
       .valid_ch(valid_ch), 
       .mac_cha(mac_cha), 
       .mac_chb(mac_chb), 
       .mac_chc(mac_chc), 
       .mac_chd(mac_chd), 
       .mac_dv(mac_dv));

    ch_fifo cha_fifo_inst 
      (.rd_clk(rd_clk_dll), 
       .wr_clk(wr_clka_dll), 
       .reset(reset), 
       .data_ch(data_cha), 
       .rd_data(rd_data_cha), 
       .rd(rd[0]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[0]), 
       .almost_full(almost_full[0]), 
       .almost_empty(almost_empty[0]),
       .full(full[0]),
       .empty(empty[0]));    

    ch_fifo chb_fifo_inst 
      (.rd_clk(rd_clk_dll), 
       .wr_clk(wr_clkb_dll), 
       .reset(reset), 
       .data_ch(data_chb), 
       .rd_data(rd_data_chb), 
       .rd(rd[1]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[1]), 
       .almost_full(almost_full[1]), 
       .almost_empty(almost_empty[1]),
       .full(full[1]),
       .empty(empty[1]));    

    ch_fifo chc_fifo_inst
      (.rd_clk(rd_clk_dll), 
       .wr_clk(wr_clkc_dll), 
       .reset(reset), 
       .data_ch(data_chc), 
       .rd_data(rd_data_chc), 
       .rd(rd[2]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[2]), 
       .almost_full(almost_full[2]), 
       .almost_empty(almost_empty[2]),
       .full(full[2]),
       .empty(empty[2]));    

    ch_fifo chd_fifo_inst 
      (.rd_clk(rd_clk_dll), 
       .wr_clk(wr_clkd_dll), 
       .reset(reset), 
       .data_ch(data_chd), 
       .rd_data(rd_data_chd), 
       .rd(rd[3]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[3]), 
       .almost_full(almost_full[3]), 
       .almost_empty(almost_empty[3]),
       .full(full[3]),
       .empty(empty[3]));    
    
    
    BUFGDLL rd_clk_inst (.I(rd_clk),.O(rd_clk_dll));
    BUFGDLL wr_clk_cha_inst (.I(wr_clk_cha),.O(wr_clka_dll));
    BUFGDLL wr_clk_chb_inst (.I(wr_clk_chb),.O(wr_clkb_dll));
    BUFGDLL wr_clk_chc_inst (.I(wr_clk_chc),.O(wr_clkc_dll));
    BUFGDLL wr_clk_chd_inst (.I(wr_clk_chd),.O(wr_clkd_dll));

endmodule // correlate_and_accumulate