cnt6bcd.vhd

这是关于VHDL时钟的源代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt6bcd is
    Port (	clkin	:in std_logic;
			co		:out std_logic;
    		qout	:out std_logic_vector(2 downto 0)
			);
end cnt6bcd;

architecture behavioral of cnt6bcd is
signal	cnt6	:std_logic_vector(2 downto 0);
begin
	process(clkin)
	begin
		if clkin'event and clkin='1' then
			if	cnt6="101"	then
				cnt6<="000";
				co<='1';
			else
				cnt6<=cnt6 + 1;
				co<='0';
			end if;
		end if;
	end process;
	qout<=cnt6;

end behavioral;