📄 iolpc2129.h
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/***************************************************************************
**
** This file defines the Special Function Registers for
** Philips LPC210x
**
** Used with ICCARM and AARM.
**
** (c) Copyright IAR Systems 2003
**
** $Revision: 1.11 $
**
** Note: Only little endian addressing of 8 bit registers.
***************************************************************************/
#ifndef __IOLPC2129_H
#define __IOLPC2129_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F) /* 0x4F = 79 dec */
#error This file should only be compiled by ICCARM/AARM
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** IOLPC210X SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************
***************************************************************************/
/* C specific declarations ************************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
/* External interrupt register */
typedef struct {
__REG32 EINT0 :1;
__REG32 EINT1 :1;
__REG32 EINT2 :1;
__REG32 EINT3 :1;
__REG32 :28;
} __extint_bits;
/* External interrupt wakeup register */
typedef struct {
__REG32 EXTWAKE0 :1;
__REG32 EXTWAKE1 :1;
__REG32 EXTWAKE2 :1;
__REG32 EXTWAKE3 :1;
__REG32 :28;
} __extwake_bits;
/* External interrupt mode register */
typedef struct {
__REG32 EXTMODE0 :1;
__REG32 EXTMODE1 :1;
__REG32 EXTMODE2 :1;
__REG32 EXTMODE3 :1;
__REG32 :28;
} __extmode_bits;
/* External interrupt polarity register */
typedef struct {
__REG32 EXTPOLAR0 :1;
__REG32 EXTPOLAR1 :1;
__REG32 EXTPOLAR2 :1;
__REG32 EXTPOLAR3 :1;
__REG32 :28;
} __extpolar_bits;
/* Memory mapping control register */
typedef struct {
__REG32 MAP :2;
__REG32 :30;
} __memmap_bits;
/* PLL control register */
typedef struct {
__REG32 PLLE :1;
__REG32 PLLC :1;
__REG32 :30;
} __pllcon_bits;
/* PLL config register */
typedef struct {
__REG32 MSEL :5;
__REG32 PSEL :2;
__REG32 :25;
} __pllcfg_bits;
/* PLL status register */
typedef struct {
__REG32 MSEL :5;
__REG32 PSEL :2;
__REG32 :1;
__REG32 PLLE :1;
__REG32 PLLC :1;
__REG32 PLOCK :1;
__REG32 :21;
} __pllstat_bits;
/* PLL feed register */
typedef struct {
__REG32 FEED :8;
__REG32 :24;
} __pllfeed_bits;
/* Power control register */
typedef struct {
__REG32 IDL :1;
__REG32 PD :1;
__REG32 :30;
} __pcon_bits;
/* Power control for peripherals register LPC2119/2129 */
typedef struct {
__REG32 :1;
__REG32 PCTIM0 :1;
__REG32 PCTIM1 :1;
__REG32 PCURT0 :1;
__REG32 PCURT1 :1;
__REG32 PCPWM0 :1;
__REG32 :1;
__REG32 PCI2C :1;
__REG32 PCSPI0 :1;
__REG32 PCRTC :1;
__REG32 PCSPI1 :1;
__REG32 :1;
__REG32 PCAD :1;
__REG32 PCCAN1 :1;
__REG32 PCCAN2 :1;
__REG32 :17;
} __pconp_bits;
/* VPB divider register */
typedef struct {
__REG32 VPBDIV :2;
__REG32 :30;
} __vpbdiv_bits;
/* Memory accelerator module control register */
typedef struct {
__REG32 MODECTRL :2;
__REG32 :30;
} __mamcr_bits;
/* Memory accelerator module timing register */
typedef struct {
__REG32 CYCLES :3;
__REG32 :29;
} __mamtim_bits;
/* VIC Interrupt registers */
typedef struct {
__REG32 INT0 :1;
__REG32 INT1 :1;
__REG32 INT2 :1;
__REG32 INT3 :1;
__REG32 INT4 :1;
__REG32 INT5 :1;
__REG32 INT6 :1;
__REG32 INT7 :1;
__REG32 INT8 :1;
__REG32 INT9 :1;
__REG32 INT10 :1;
__REG32 INT11 :1;
__REG32 INT12 :1;
__REG32 INT13 :1;
__REG32 INT14 :1;
__REG32 INT15 :1;
__REG32 INT16 :1;
__REG32 INT17 :1;
__REG32 INT18 :1;
__REG32 INT19 :1;
__REG32 INT20 :1;
__REG32 INT21 :1;
__REG32 INT22 :1;
__REG32 INT23 :1;
__REG32 INT24 :1;
__REG32 INT25 :1;
__REG32 INT26 :1;
__REG32 INT27 :1;
__REG32 INT28 :1;
__REG32 INT29 :1;
__REG32 INT30 :1;
__REG32 INT31 :1;
} __vicint_bits;
/* VIC Vector control registers */
typedef struct {
__REG32 NUMBER :5;
__REG32 ENABLED :1;
__REG32 :26;
} __vicvectcntl_bits;
/* VIC protection enable register */
typedef struct {
__REG32 PROTECT :1;
__REG32 :31;
} __vicprotection_bits;
/* Pin function select register 0 */
typedef struct {
__REG32 P0_0 :2;
__REG32 P0_1 :2;
__REG32 P0_2 :2;
__REG32 P0_3 :2;
__REG32 P0_4 :2;
__REG32 P0_5 :2;
__REG32 P0_6 :2;
__REG32 P0_7 :2;
__REG32 P0_8 :2;
__REG32 P0_9 :2;
__REG32 P0_10 :2;
__REG32 P0_11 :2;
__REG32 P0_12 :2;
__REG32 P0_13 :2;
__REG32 P0_14 :2;
__REG32 P0_15 :2;
} __pinsel0_bits;
/* Pin function select register 1 */
typedef struct {
__REG32 P0_16 :2;
__REG32 P0_17 :2;
__REG32 P0_18 :2;
__REG32 P0_19 :2;
__REG32 P0_20 :2;
__REG32 P0_21 :2;
__REG32 P0_22 :2;
__REG32 P0_23 :2;
__REG32 P0_24 :2;
__REG32 P0_25 :2;
__REG32 P0_26 :2;
__REG32 P0_27 :2;
__REG32 P0_28 :2;
__REG32 P0_29 :2;
__REG32 P0_30 :2;
__REG32 P0_31 :2;
} __pinsel1_bits;
/* GPIO register 0 */
typedef struct {
__REG32 P0_0 :1;
__REG32 P0_1 :1;
__REG32 P0_2 :1;
__REG32 P0_3 :1;
__REG32 P0_4 :1;
__REG32 P0_5 :1;
__REG32 P0_6 :1;
__REG32 P0_7 :1;
__REG32 P0_8 :1;
__REG32 P0_9 :1;
__REG32 P0_10 :1;
__REG32 P0_11 :1;
__REG32 P0_12 :1;
__REG32 P0_13 :1;
__REG32 P0_14 :1;
__REG32 P0_15 :1;
__REG32 P0_16 :1;
__REG32 P0_17 :1;
__REG32 P0_18 :1;
__REG32 P0_19 :1;
__REG32 P0_20 :1;
__REG32 P0_21 :1;
__REG32 P0_22 :1;
__REG32 P0_23 :1;
__REG32 P0_24 :1;
__REG32 P0_25 :1;
__REG32 P0_26 :1;
__REG32 P0_27 :1;
__REG32 P0_28 :1;
__REG32 P0_29 :1;
__REG32 P0_30 :1;
__REG32 P0_31 :1;
} __gpio0_bits;
/* GPIO register 1 */
typedef struct {
__REG32 P1_0 :1;
__REG32 P1_1 :1;
__REG32 P1_2 :1;
__REG32 P1_3 :1;
__REG32 P1_4 :1;
__REG32 P1_5 :1;
__REG32 P1_6 :1;
__REG32 P1_7 :1;
__REG32 P1_8 :1;
__REG32 P1_9 :1;
__REG32 P1_10 :1;
__REG32 P1_11 :1;
__REG32 P1_12 :1;
__REG32 P1_13 :1;
__REG32 P1_14 :1;
__REG32 P1_15 :1;
__REG32 P1_16 :1;
__REG32 P1_17 :1;
__REG32 P1_18 :1;
__REG32 P1_19 :1;
__REG32 P1_20 :1;
__REG32 P1_21 :1;
__REG32 P1_22 :1;
__REG32 P1_23 :1;
__REG32 P1_24 :1;
__REG32 P1_25 :1;
__REG32 P1_26 :1;
__REG32 P1_27 :1;
__REG32 P1_28 :1;
__REG32 P1_29 :1;
__REG32 P1_30 :1;
__REG32 P1_31 :1;
} __gpio1_bits;
/* UART interrupt enable register */
typedef struct {
__REG8 RDAIE :1;
__REG8 THREIE :1;
__REG8 RXLSIE :1;
__REG8 :5;
} __uartier0_bits;
/* UART interrupt enable register */
typedef struct {
__REG8 RDAIE :1;
__REG8 THREIE :1;
__REG8 RXLSIE :1;
__REG8 MSIE :1;
__REG8 :4;
} __uartier1_bits;
/* UART interrupt identification register and fifo control register */
typedef union {
//UxIIR
struct {
__REG8 IP :1;
__REG8 IID :3;
__REG8 :2;
__REG8 IIRFE :2;
};
//UxFCR
struct {
__REG8 FCRFE :1;
__REG8 RFR :1;
__REG8 TFR :1;
__REG8 :3;
__REG8 RTLS :2;
};
} __uartfcriir_bits;
/* UART line control register */
typedef struct {
__REG8 WLS :2;
__REG8 SBS :1;
__REG8 PE :1;
__REG8 PS :2;
__REG8 BC :1;
__REG8 DLAB :1;
} __uartlcr_bits;
/* UART modem control register */
typedef struct {
__REG8 DTR :1;
__REG8 RTS :1;
__REG8 :2;
__REG8 LMS :1;
__REG8 :3;
} __uartmcr_bits;
/* UART line status register */
typedef struct {
__REG8 DR :1;
__REG8 OE :1;
__REG8 PE :1;
__REG8 FE :1;
__REG8 BI :1;
__REG8 THRE :1;
__REG8 TEMT :1;
__REG8 RXFE :1;
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